Xilinx Spartan-3E User Manual page 105

R
Table 13-1: FPGA-to-DDR SDRAM Connections (Continued)
Spartan-3E Starter Kit Board User Guide
UG230 (v1.0) March 9, 2006
DDR SDRAM
Category Signal Name
SD_DQ15
SD_DQ14
SD_DQ13
SD_DQ12
SD_DQ11
SD_DQ10
SD_DQ9
SD_DQ8
SD_DQ7
SD_DQ6
SD_DQ5
SD_DQ4
SD_DQ3
SD_DQ2
SD_DQ1
SD_DQ0
SD_BA1
SD_BA0
SD_RAS
SD_CAS
SD_WE
SD_CK_N
SD_CK_P
SD_CKE
SD_CS
SD_UDM
SD_LDM
SD_UDQS
SD_LDQS
SD_CK_FB
www.xilinx.com
FPGA Pin
Number
H5 Data input/output
H6
G5
G6
F2
F1
E1
E2
M6
M5
M4
M3
L4
L3
L1
L2
K6 Bank address inputs
K5
C1 Command inputs
C2
D1
J4 Differential clock input
J5
K3 Active-High clock enable input
K4 Active-Low chip select input
J1 Data Mask. Upper and Lower data masks
J2
G3 Data Strobe. Upper and Lower data strobes
L6
B9 SDRAM clock feedback into top DCM
within FPGA. Used by some DDR SDRAM
controller cores
DDR SDRAM Connections
Function
105