Chapter 13: Ddr Sdram - Xilinx Spartan-3E User Manual

R
DDR SDRAM
The Spartan-3E Starter Kit boards includes a 512 Mbit (32M x 16) Micron Technology DDR
SDRAM (MT46V32M16) with a 16-bit data interface, as shown in
SDRAM interface pins connect to the FPGA's I/O Bank 3 on the FPGA. I/O Bank 3 and the
DDR SDRAM are both powered by 2.5V, generated by an LTC3412 regulator from the
board's 5V supply input. The 1.25V reference voltage, common to the FPGA and DDR
SDRAM, is generated using a resistor voltage divider from the 2.5V rail.
5.0V
LTC3412
Figure 13-1: FPGA Interface to Micron 512 Mbit DDR SDRAM
All DDR SDRAM interface signals are terminated.
Spartan-3E Starter Kit Board User Guide
UG230 (v1.0) March 9, 2006
2.5V
1.25V
Spartan-3E FPGA
See Table
VREF See Table
VCCO_3 See Table
(C1)
(C2)
(D1)
(J1)
(J2)
(G3)
(L6)
(K4)
(K3)
(J4)
(B9) GCLK9 (J5)
SD_CK_FB
www.xilinx.com
Micron 512 Mb DDR SDRAM
SD_A<12:0>
A[12:0]
SD_DQ<15:0>
DQ[15:0]
SD_BA<1:0>
BA[1:0]
SD_RAS
RAS#
SD_CAS
CAS#
SD_WE
WE#
SD_UDM
UQM
SD_LDM
LQM
SD_UDQS
UDQS
SD_LDQS
LDQS
SD_CS
CS#
SD_CKE
CKE
SD_CK_N
CK#
SD_CK_P
CK
Chapter 13
Figure 13-1. All DDR
VREF
VDD
VDDQ
MT46V32M16
(32Mx16)
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