Control; Reserve Fpga Vref Pins; Related Resources - Xilinx Spartan-3E User Manual

R

Control

Figure 13-4
control pins, including the I/O pin assignment and the I/O standard used.

Reserve FPGA VREF Pins

Five pins in I/O Bank 3 are dedicated as voltage reference inputs, VREF. These pins cannot
be used for general-purpose I/O in a design. Prohibit the software from using these pins
with the constraints provided in
5i

Related Resources

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Spartan-3E Starter Kit Board User Guide
UG230 (v1.0) March 9, 2006
provides the User Constraint File (UCF) constraints for the DDR SDRAM
NET "SD_BA<0>" LOC = "K5" |
NET "SD_BA<1>" LOC = "K6" |
NET "SD_CAS" LOC = "C2" |
NET "SD_CK_N" LOC = "J4" |
NET "SD_CK_P" LOC = "J5" |
NET "SD_CKE" LOC = "K3" |
NET "SD_CS" LOC = "K4" |
NET "SD_LDM" LOC = "J2" |
NET "SD_LDQS" LOC = "L6" |
NET "SD_RAS" LOC = "C1" |
NET "SD_UDM" LOC = "J1" |
NET "SD_UDQS" LOC = "G3" |
NET "SD_WE" LOC = "D1" |
# Path to allow connection to top DCM connection
NET "SD_CK_FB" LOC = "B9" |
Figure 13-4: UCF Location Constraints for DDR SDRAM Control Pins
# Prohibit VREF pins
CONFIG PROHIBIT = D2;
CONFIG PROHIBIT = G4;
CONFIG PROHIBIT = J6;
CONFIG PROHIBIT = L5;
CONFIG PROHIBIT = R4;
Figure 13-5: UCF Location Constraints for StrataFlash Control Pins
Xilinx Embedded Design Kit (EDK)
http://www.xilinx.com/ise/embedded_design_prod/platform_studio.htm
MT46V32M16 (32M x 16) DDR SDRAM Data Sheet
http://download.micron.com/pdf/datasheets/dram/ddr/512MBDDRx4x8x16.pdf
MicroBlaze OPB Double Data Rate (DDR) SDRAM Controller (v2.00b)
http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_ddr.pdf
www.xilinx.com
IOSTANDARD = SSTL2_I ;
IOSTANDARD = SSTL2_I ;
IOSTANDARD = SSTL2_I ;
IOSTANDARD = SSTL2_I ;
IOSTANDARD = SSTL2_I ;
IOSTANDARD = SSTL2_I ;
IOSTANDARD = SSTL2_I ;
IOSTANDARD = SSTL2_I ;
IOSTANDARD = SSTL2_I ;
IOSTANDARD = SSTL2_I ;
IOSTANDARD = SSTL2_I ;
IOSTANDARD = SSTL2_I ;
IOSTANDARD = SSTL2_I ;
IOSTANDARD = LVCMOS33 ;
Figure 13-5.
Related Resources
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