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Chapter 10: Analog Capture Circuit
Table 10-2: Programmable Gain Settings for Pre-Amplifier (Continued)
SPI Control Interface
Figure 10-3
for each amplifier is sent as an 8-bit command word, consisting of two 4-bit fields. The
most-significant bit, B3, is sent first.
The AMP_DOUT output from the amplifier echoes the previous gain settings. These
values can be ignored for most applications.
The SPI bus transaction starts when the FPGA asserts AMP_CS Low (see
amplifier captures serial data on SPI_MOSI on the rising edge of the SPI_SCK clock signal.
The amplifier presents serial data on AMP_DOUT on the falling edge of SPI_SCK.
AMP_CS
30
SPI_SCK
SPI_MOSI
7
(from FPGA)
AMP_DOUT
Previous 7
(from AMP)
Figure 10-4: SPI Timing When Communicating with Amplifier
76
A3
Gain
B3
-5
0
-10
0
-20
0
-50
0
-100
0
highlights the SPI-based communications interface with the amplifier. The gain
AMP_DOUT
SPI_MOSI
Spartan-3E
AMP_CS
FPGA
SPI_SCK
Master
Figure 10-3: SPI Serial Interface to Amplifier
30
6
5
85 max
6
All timing is minimum in nanoseconds unless otherwise noted.
www.xilinx.com
A2
A1
A0
B2
B1
B0
0
1
1
0
1
0
1
1
1
1
Slave: LTC2624-1
0
A
A
A
A
0
1
2
3
A Gain
50
4
3
5
4
Spartan-3E Starter Kit Board User Guide
Input Voltage Range
Minimum
Maximum
1
1.4
1.9
0
1.525
1.775
1
1.5875
1.7125
0
1.625
1.675
1
1.6375
1.6625
7
B
B
B
B
0
1
2
3
B Gain
UG230_c10_03_030306
Figure
10-4). The
50
2
3
2
UG230_c10_04_022306
UG230 (v1.0) March 9, 2006
R
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