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Xilinx SP623 User Manual

Xilinx SP623 User Manual

Spartan-6 fpga gtp transceiver characterization board
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SP623
Spartan-6 FPGA
GTP Transceiver
Characterization Board
User Guide
UG751 (v1.0) May 22, 2010

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Summary of Contents for Xilinx SP623

  • Page 1 SP623 Spartan-6 FPGA GTP Transceiver Characterization Board User Guide UG751 (v1.0) May 22, 2010...

  • Page 2: Revision History

    Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.

  • Page 3: Table Of Contents

    Online Document ............6 Chapter 1: SP623 Board Features and Operation SP623 Board Features .
  • Page 4 SP623 Board User Guide UG751 (v1.0) May 22, 2010...

  • Page 5: Preface: About This Guide

    Preface About This Guide This document describes the basic setup, features, and operation of the SP623 Spartan-6® FPGA GTP transceiver characterization board. The SP623 board provides the hardware environment for characterizing and evaluating the GTP transceivers available on the Spartan-6 XC6SLX150T-3FGG676 FPGA.

  • Page 6: Online Document

    Blue text in the current document Refer to “Title Formats” in Chapter 1 for details. Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest speed files. www.xilinx.com SP623 Board User Guide UG751 (v1.0) May 22, 2010...

  • Page 7: Chapter 1: Sp623 Board Features And Operation

    The SP623 board block diagram is shown in Figure 1-1. Caution! The SP623 board can be damaged by electrostatic discharge (ESD). Follow standard ESD prevention measures when handling the board. SP623 Board User Guide www.xilinx.com UG751 (v1.0) May 22, 2010...

  • Page 8: Detailed Description

    SuperClock-2 Module UG751_c1_01_050410 Figure 1-1: SP623 Board Block Diagram Detailed Description Figure 1-2 shows the SP623 board described in this user guide. Each numbered feature that is referenced in Figure 1-2 is described in the sections that follow. Note: The image in...
  • Page 9 INIT LED (DS20) 20a FMC1 (J112) System ACE controller (U25) 20b FMC2 (J113) System ACE reset, active-Low (SW2) I2C bus management (U14) UG751_c1_02_041310 Figure 1-2: Detailed Description of SP623 Board Components SP623 Board User Guide www.xilinx.com UG751 (v1.0) May 22, 2010...

  • Page 10: Power Management

    Do NOT apply power to J122 and connectors J141 and/or J234 at the same time. Doing so will damage the SP623 board. The SP623 board power is turned on or off by switch SW1. When the switch is in the ON position, power is applied to the board and a green LED (DS36) illuminates.

  • Page 11: Onboard Power Regulation

    MGTAVTT UG751_c1_03_041510 Figure 1-3: SP623 Board Power Supply Block Diagram The SP623 board uses power regulators and PMBus compliant digital PWM system controllers from Texas Instruments to supply the core and auxiliary voltages listed in Table 1-1. The board can also be configured to use external bench power supply for each voltage.
  • Page 12 Chapter 1: SP623 Board Features and Operation Table 1-1: Onboard Power System Devices Power External Reference Power Rail Typical Device Description Regulation Supply Designator Net Name Voltage Jumper Jack Core voltage controller and regulators UCD9240PFC PMBus compliant digital PWM system...

  • Page 13: Gtp Transceiver Power Module

    The GTP transceiver power module supplies MGTAVCC and MGTAVTT voltages to the FPGA GTP transceivers. Two power modules are provided with the SP623 board. Either of the power modules can be plugged into connectors J34 and J179 in the outlined and labeled...

  • Page 14: Fpga Configuration

    Chapter 1: SP623 Board Features and Operation Linear Technology Module is installed, place jumpers on JP1 and/or JP2 across pins 2–3 (OFF position). Note: The power regulation jumper must be placed in the OFF position before connecting an external supply to its corresponding supply jack.

  • Page 15: Prog Push Button

    The DONE LED (DS6) indicates the status of the DONE pin of the FPGA. When the DONE pin is high, DS6 lights indicating the FPGA is successfully configured. INIT LED [Figure 1-2, callout 5] The INIT LED (DS20) lights during FPGA initialization. SP623 Board User Guide www.xilinx.com UG751 (v1.0) May 22, 2010...

  • Page 16: System Ace Controller

    Chapter 1: SP623 Board Features and Operation System ACE Controller [Figure 1-2, callout 6] The onboard System ACE controller (U25) allows storage of multiple configuration files on a CompactFlash card. These configuration files can be used to program the FPGA. The CompactFlash card connects to the CompactFlash card connector (U24) located directly below the System ACE controller on the back-side of the board.

  • Page 17: 200 Mhz 2.5V Lvds Oscillator

    J196 200 MHz 2.5V LVDS Oscillator [Figure 1-2, callout 10] The SP623 board has one 2.5V LVDS differential 200 MHz oscillator (U7) connected to the FPGA global clock inputs. Table 1-5 lists the FPGA pin connections to the LVDS oscillator.
  • Page 18 Chapter 1: SP623 Board Features and Operation Table 1-6: SuperClock-2 FPGA I/O Mapping FPGA Pin Net Name J32 Pin CM_LVDS1_P CM_LVDS1_N CM_LVDS2_P CM_LVDS2_N CM_LVDS3_P CM_LVDS3_N CM_GCLK_P CM_GCLK_N CM_CTRL_0 CM_CTRL_1 AA24 CM_CTRL_2 AA23 CM_CTRL_3 CM_CTRL_4 CM_CTRL_5 CM_CTRL_6 CM_CTRL_7 AE26 CM_CTRL_8 AE25...

  • Page 19: User Sma Global Clock Inputs

    [Figure 1-2, callout 12] The SP623 board provides two single-ended clock input SMAs that can be used for connecting to an external function generator. These clock inputs can alternatively be used as a differential pair. The FPGA clock pins are connected to the SMAs as shown in Table 1-7.

  • Page 20: User Push Buttons (Active High)

    Chapter 1: SP623 Board Features and Operation Table 1-9: User DIP Switches Reference FPGA Pin Net Name Designator User Push Buttons (Active High) [Figure 1-2, callout 15] SW5 and SW6 are active-High user push buttons that are connected to user I/O pins on the...

  • Page 21: Gtp Transceiver Pins

    Figure 1-8: GTP Transceiver and Reference Clock SMA Locations Table 1-12: GTP Transceiver Pins FGPA Pin Net Name SMA Connector Trace Length (Mils) 101_RX0_P 4,253 101_RX0_N 4,253 101_TX0_P 3,634 101_TX0_N 3,633 101_RX1_P 3,861 101_RX1_N 3,861 SP623 Board User Guide www.xilinx.com UG751 (v1.0) May 22, 2010...
  • Page 22 Chapter 1: SP623 Board Features and Operation Table 1-12: GTP Transceiver Pins (Cont’d) FGPA Pin Net Name SMA Connector Trace Length (Mils) 101_TX1_P 2,503 101_TX1_N 2,502 123_RX0_P 3,531 123_RX0_N 3,531 123_TX0_P 3,340 123_TX0_N 3,340 123_RX1_P 3,665 123_RX1_N 3,664 123_TX1_P 2,939...

  • Page 23: Gtp Transceiver Clock Input Smas

    [Figure 1-2, callout 18] The SP623 board provides differential SMA connectors that can be used for connecting an external function generator to all GTP transceiver reference clock inputs of the FPGA. The FPGA reference clock pins are connected to the SMA connectors as shown in Table 1-13.

  • Page 24: Fmc Hpc Connectors

    Chapter 1: SP623 Board Features and Operation The CP2103 supports an IO voltage range of 1.8V to 2.5V on the SP623 board. The connections between the FPGA and CP2103 should use the LVCMOS25 IO standard. UART IP (for example, Xilinx® XPS UART Lite) must be implemented in the FPGA fabric.
  • Page 25 FMC HPC connectors on the SP623 board is fixed at 2.5V (non-adjustable). The 2.5V rail cannot be turned off. The VITA 57.1 FMC interfaces on the SP623 board are compatible with 2.5V mezzanine cards capable of supporting 2.5V V...
  • Page 26 Chapter 1: SP623 Board Features and Operation Table 1-17: Vita 57.1 FMC1 HPC Connections at J112 (Cont’d) FPGA Pin Net Name FMC Pin FMC1_HA09_P FMC1_HA09_N FMC1_HA10_P FMC1_HA10_N FMC1_HA11_P FMC1_HA11_N FMC1_HA12_P FMC1_HA12_N FMC1_HA13_P FMC1_HA13_N FMC1_HA14_P FMC1_HA14_N FMC1_HA15_P FMC1_HA15_N FMC1_HA16_P FMC1_HA16_N FMC1_HA17_CC_P...
  • Page 27 FMC1_LA02_P FMC1_LA02_N FMC1_LA03_P FMC1_LA03_N FMC1_LA04_P FMC1_LA04_N FMC1_LA05_P FMC1_LA05_N FMC1_LA06_P FMC1_LA06_N FMC1_LA07_P FMC1_LA07_N FMC1_LA08_P FMC1_LA08_N FMC1_LA09_P FMC1_LA09_N FMC1_LA10_P FMC1_LA10_N FMC1_LA11_P FMC1_LA11_N FMC1_LA12_P FMC1_LA12_N FMC1_LA13_P FMC1_LA13_N FMC1_LA14_P FMC1_LA14_N FMC1_LA15_P FMC1_LA15_N FMC1_LA16_P FMC1_LA16_N SP623 Board User Guide www.xilinx.com UG751 (v1.0) May 22, 2010...
  • Page 28 Chapter 1: SP623 Board Features and Operation Table 1-17: Vita 57.1 FMC1 HPC Connections at J112 (Cont’d) FPGA Pin Net Name FMC Pin FMC1_LA17_CC_P FMC1_LA17_CC_N FMC1_LA18_CC_P FMC1_LA18_CC_N FMC1_LA19_P FMC1_LA19_N FMC1_LA20_P FMC1_LA20_N FMC1_LA21_P FMC1_LA21_N FMC1_LA22_P FMC1_LA22_N FMC1_LA23_P FMC1_LA23_N FMC1_LA24_P FMC1_LA24_N FMC1_LA25_P...
  • Page 29 Table 1-18: Vita 57.1 FMC2 HPC Connections at J113 FPGA Pin Net Name FMC Pin FMC2_CLK0_M2C_P FMC2_CLK0_M2C_N AD14 FMC2_CLK1_M2C_P AF14 FMC2_CLK1_M2C_N FMC2_HA00_CC_P FMC2_HA00_CC_N FMC2_HA02_P FMC2_HA02_N FMC2_HA03_P FMC2_HA03_N FMC2_HA04_P FMC2_HA04_N FMC2_HA05_P FMC2_HA05_N FMC2_HA06_P FMC2_HA06_N FMC2_HA07_P FMC2_HA07_N FMC2_HA08_P FMC2_HA08_N FMC2_HA09_P SP623 Board User Guide www.xilinx.com UG751 (v1.0) May 22, 2010...
  • Page 30 Chapter 1: SP623 Board Features and Operation Table 1-18: Vita 57.1 FMC2 HPC Connections at J113 (Cont’d) FPGA Pin Net Name FMC Pin FMC2_HA09_N FMC2_HA10_P FMC2_HA10_N FMC2_HA11_P FMC2_HA11_N FMC2_HA12_P FMC2_HA12_N FMC2_HA13_P FMC2_HA13_N FMC2_HA14_P FMC2_HA14_N FMC2_HA15_P FMC2_HA15_N FMC2_HA16_P FMC2_HA16_N FMC2_HA17_CC_P FMC2_HA17_CC_N...
  • Page 31 FMC2_LA07_P AB19 FMC2_LA07_N FMC2_LA08_P FMC2_LA08_N AA18 FMC2_LA09_P AB17 FMC2_LA09_N FMC2_LA10_P AA16 FMC2_LA10_N FMC2_LA11_P FMC2_LA11_N FMC2_LA12_P FMC2_LA12_N AA15 FMC2_LA13_P AB15 FMC2_LA13_N FMC2_LA14_P AA22 FMC2_LA14_N FMC2_LA15_P AA12 FMC2_LA15_N FMC2_LA16_P FMC2_LA16_N AE15 FMC2_LA17_CC_P SP623 Board User Guide www.xilinx.com UG751 (v1.0) May 22, 2010...
  • Page 32 Chapter 1: SP623 Board Features and Operation Table 1-18: Vita 57.1 FMC2 HPC Connections at J113 (Cont’d) FPGA Pin Net Name FMC Pin AF15 FMC2_LA17_CC_N AD23 FMC2_LA18_CC_P AF23 FMC2_LA18_CC_N FMC2_LA19_P AA11 FMC2_LA19_N FMC2_LA20_P FMC2_LA20_N FMC2_LA21_P FMC2_LA21_N AA10 FMC2_LA22_P AB11 FMC2_LA22_N...

  • Page 33: I 2 C Bus Management

    C component can be accessed by selecting the appropriate channel through the control register of the MUX as shown in Table 1-20. Table 1-20: I C Channel Assignments C Component Channel SuperClock-2 module GTP transceiver power supply module FMC1 FMC2 SP623 Board User Guide www.xilinx.com UG751 (v1.0) May 22, 2010...
  • Page 34 Chapter 1: SP623 Board Features and Operation www.xilinx.com SP623 Board User Guide UG751 (v1.0) May 22, 2010...
  • Page 35 SYSTEM ACE CLOCK Installed 1–2 (ON) SYSACE JTAG ENABLE Installed 1–2 SYSACE JTAG ENABLE Installed 1–2 J195 SYSACE JTAG ENABLE Installed 1–2 J196 SYSACE JTAG ENABLE Installed 1–2 FMC1 JTAG Installed 2–3 SP623 Board User Guide www.xilinx.com UG751 (v1.0) May 22, 2010...
  • Page 36 These entries are not visible in the PCB silkscreen labels. Table A-2: Digital Power Shorting Plugs Shorting Plug Connector Name Position MGTAVCCPLL Installed VCC3V3 Installed VCC2V5 Installed J102 VCCINT Installed J104 VCCAUX Installed J105 VCCO Installed www.xilinx.com SP623 Board User Guide UG751 (v1.0) May 22, 2010...
  • Page 37 HB17_P_CC HB18_N LA32_P LA33_N HB20_P HB21_N 12P0V DP6_C2M_N HB17_N_CC LA32_N HB20_N 3P3V DP5_C2M_P VIO_B_M2C VADJ VADJ 3P3V DP5_C2M_N VIO_B_M2C VADJ VADJ 3P3V RES0 UG751_aB_01_041310 Figure B-1: FMC HPC Connector Pinout SP623 Board User Guide www.xilinx.com UG751 (v1.0) May 22, 2010...
  • Page 38 Appendix B: VITA 57.1 FMC HPC Connector Pinout www.xilinx.com SP623 Board User Guide UG751 (v1.0) May 22, 2010...
  • Page 39 Appendix C SP623 Master UCF Listing The SP623 master user constraints file (UCF) template provides for designs targeting the SP623 Spartan-6 FPGA GTP transceiver characterization board. Net names in the constraints listed below correlate with net names on the SP623 board schematic. Users must identify the appropriate pins and replace the net names below with net names in the user RTL.
  • Page 40 Appendix C: SP623 Master UCF Listing NET "245_RX1_P "LOC = "AC10"; NET "245_TX0_N "LOC = "AF7"; NET "245_TX0_P "LOC = "AE7"; NET "245_TX1_N "LOC = "AF9"; NET "245_TX1_P "LOC = "AE9"; NET "267_REFCLK0_N "LOC = "AD16"; NET "267_REFCLK0_P "LOC = "AC16";...
  • Page 41 NET "FMC1_HA20_P "LOC = "G4"; NET "FMC1_HA21_N "LOC = "J7"; NET "FMC1_HA21_P "LOC = "J9"; NET "FMC1_HA22_N "LOC = "C1"; NET "FMC1_HA22_P "LOC = "C2"; NET "FMC1_HA23_N "LOC = "K8"; SP623 Board User Guide www.xilinx.com UG751 (v1.0) May 22, 2010...
  • Page 42 Appendix C: SP623 Master UCF Listing NET "FMC1_HA23_P "LOC = "K9"; NET "FMC1_LA00_CC_N "LOC = "D13"; NET "FMC1_LA00_CC_P "LOC = "E13"; NET "FMC1_LA01_CC_N "LOC = "A13"; NET "FMC1_LA01_CC_P "LOC = "C13"; NET "FMC1_LA02_N "LOC = "G9"; NET "FMC1_LA02_P "LOC = "H9";...
  • Page 43 NET "FMC2_HA20_N "LOC = "N4"; NET "FMC2_HA20_P "LOC = "N5"; NET "FMC2_HA21_N "LOC = "N9"; NET "FMC2_HA21_P "LOC = "P10"; NET "FMC2_HA22_N "LOC = "M9"; NET "FMC2_HA22_P "LOC = "M10"; SP623 Board User Guide www.xilinx.com UG751 (v1.0) May 22, 2010...
  • Page 44 Appendix C: SP623 Master UCF Listing NET "FMC2_HA23_N "LOC = "Y5"; NET "FMC2_HA23_P "LOC = "Y6"; NET "FMC2_LA00_CC_N "LOC = "AC14"; NET "FMC2_LA00_CC_P "LOC = "AB14"; NET "FMC2_LA01_CC_N "LOC = "AF13"; NET "FMC2_LA01_CC_P "LOC = "AE13"; NET "FMC2_LA02_N "LOC = "W19";...
  • Page 45 NET "USB_GPIO2 "LOC = "N22"; NET "USB_GPIO3 "LOC = "N21"; NET "USB_RTS "LOC = "L24"; NET "USB_RX "LOC = "N20"; NET "USB_TX "LOC = "N19"; NET "VFS "LOC = "W22"; SP623 Board User Guide www.xilinx.com UG751 (v1.0) May 22, 2010...
  • Page 46 Appendix C: SP623 Master UCF Listing www.xilinx.com SP623 Board User Guide UG751 (v1.0) May 22, 2010...
  • Page 47 Appendix D References Additional information relevant to Spartan®-6 devices, the SP623 Spartan-6 FPGA GTP transceiver characterization board, and intellectual property is available in the documents listed here: • DS162, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics • UG380, Spartan-6 FPGA Configuration User Guide •...
  • Page 48 Appendix D: References www.xilinx.com SP623 Board User Guide UG751 (v1.0) May 22, 2010...

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