Xilinx SP623 Getting Started Manual
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Xilinx SP623 Getting Started Manual

Xilinx SP623 Getting Started Manual

Ibert demonstration settings
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SP623 IBERT
Getting Started Guide
(ISE 11.4)
UG752 (v1.0.1) January 26, 2011

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Summary of Contents for Xilinx SP623

  • Page 1 SP623 IBERT Getting Started Guide (ISE 11.4) UG752 (v1.0.1) January 26, 2011...

  • Page 2: Revision History

    Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights you may require for any implementation based on the Information.

  • Page 3: Table Of Contents

    Setting Up the SP623 Board ........
  • Page 4 SP623 IBERT Getting Started Guide UG752 (v1.0.1) January 26, 2011...

  • Page 5: Sp623 Ibert

    Setting Up the ChipScope Pro Analyzer Tool. Running the IBERT Demonstration. The SP623 board is described in detail in UG751, SP623 Spartan-6 FPGA GTP Transceiver Characterization Board User Guide. Requirements The equipment and software required to run the demonstration are: •...

  • Page 6: Procedure

    The ChipScope Pro Analyzer .cpj project files for the IBERT demonstration are located on the CompactFlash memory card that is provided with the SP623 board. The project files are used to load pre-saved MGT/IBERT and clock module control settings for the demonstration.

  • Page 7: Setting Up The Sp623 Board

    Install the GTP transceiver power module: Plug the module into connectors J34 and J179. b. Remove DCPS ENABLE jumpers at J184 and J185 located on the SP623 board. Verify the four SYSACE JTAG ENABLE jumpers are installed at locations J22, J23, J195, and J196 on the SP623 board.
  • Page 8 Figure 3 shows the location of the differential clock SMA connector pairs on the SuperClock-2 module which connect to the GTP transceiver reference clocks on the SP623 board. For the IBERT demonstration, the frequencies of both output clocks from the SuperClock-2 module are the same.

  • Page 9: Running The Ibert Demonstration For Duals 101 And 123

    Table 1 and use four SMA cables to connect the output clock SMAs from the SuperClock-2 module to the reference clock SMAs of GTP Duals 101 and 123 on the SP623 board. In other words, for each row in Table 1, connect the source SMA with its corresponding destination SMA.

  • Page 10: Configuring The Fpga

    Figure 4: SMA Cable Connections for Dual 101 and 123 Transceivers and Clocks Configuring the FPGA Plug the 12V output from the power supply into connector J122. Connect the SP623 board to the Host PC. Either of these cables may be used for this connection: •...

  • Page 11: Setting Up The Chipscope Pro Analyzer Tool

    The .cpj file loads pre-saved project settings for the demonstration including MGT/ IBERT and clock module control parameters. For more information regarding MGT/IBERT settings, refer to UG029, ChipScope Pro Software and Cores User Guide. SP623 IBERT Getting Started Guide www.xilinx.com UG752 (v1.0.1) January 26, 2011...
  • Page 12 Figure 9: Project Panel Starting the Clock Module The IBERT demonstration design uses a ChipScope VIO core to control the clocks on the SuperClock-2 module. The SuperClock-2 module features two clock-source components: www.xilinx.com SP623 IBERT Getting Started Guide UG752 (v1.0.1) January 26, 2011...
  • Page 13 156.25 MHz. Typing in a different address changes the frequency of the GTP transceiver reference clocks. A complete list of frequency options and their associated ROM addresses is provided in Table 5, page SP623 IBERT Getting Started Guide www.xilinx.com UG752 (v1.0.1) January 26, 2011...

  • Page 14: Running The Ibert Demonstration

    Running the IBERT Demonstration After completing step 5 Starting the Clock Module, the IBERT demonstration is configured and running as indicated by the MGT/IBERT Settings tab within the IBERT Console. www.xilinx.com SP623 IBERT Getting Started Guide UG752 (v1.0.1) January 26, 2011...
  • Page 15 Note the line rate is 3.125 Gb/s for all four GTP transceivers (MGT Link Status in Figure 15). X-Ref Target - Figure 15 UG752_15_052510 Figure 15: GTP Transceiver Link Status SP623 IBERT Getting Started Guide www.xilinx.com UG752 (v1.0.1) January 26, 2011...
  • Page 16 Note the GTP transmitter differential output swing is preset to 595 mV (0011) as shown in Figure X-Ref Target - Figure 16 UG752_16_052510 Figure 16: GTP Transceiver TX Differential Output Swing www.xilinx.com SP623 IBERT Getting Started Guide UG752 (v1.0.1) January 26, 2011...
  • Page 17 Close the ChipScope Pro Analyzer tool. Note: Do not save changes to the project. Remove power to the SP623 board by placing SW1 in the OFF position. Remove the SMA cables from the SP623 board. SP623 IBERT Getting Started Guide www.xilinx.com...

  • Page 18: Running The Ibert Demonstration For Duals 245 And 267

    Table 3 and use four SMA cables to connect the output clock SMAs from the SuperClock-2 module to the reference clock SMAs of GTP Duals 245 and 267 on the SP623 board. In other words, for each row in Table 3, connect the source SMA with its corresponding destination SMA.

  • Page 19: Configuring The Fpga

    Figure 18: SMA Cable Connections for Dual 245 and 267 Transceivers and Clocks Configuring the FPGA Plug the 12V output from the power supply into connector J122. Connect the SP623 board to the Host PC. Either of these cables may be used for this connection: •...

  • Page 20: Setting Up The Chipscope Pro Analyzer Tool

    The .cpj file loads pre-saved project settings for the demonstration including MGT/ IBERT and clock module control parameters. For more information regarding MGT/IBERT settings, refer to UG029, ChipScope Pro Software and Cores User Guide. www.xilinx.com SP623 IBERT Getting Started Guide UG752 (v1.0.1) January 26, 2011...
  • Page 21 Figure 23: Project Panel Starting the Clock Module The IBERT demonstration design uses a ChipScope VIO core to control the clocks on the SuperClock-2 module. The SuperClock-2 module features two clock-source components: SP623 IBERT Getting Started Guide www.xilinx.com UG752 (v1.0.1) January 26, 2011...
  • Page 22 156.25 MHz. Typing in a different address changes the frequency of the GTP transceiver reference clocks. A complete list of frequency options and their associated ROM addresses is provided in Table 5, page www.xilinx.com SP623 IBERT Getting Started Guide UG752 (v1.0.1) January 26, 2011...

  • Page 23: Running The Ibert Demonstration

    Running the IBERT Demonstration After completing step 5 Starting the Clock Module, the IBERT demonstration is configured and running as indicated by the MGT/IBERT Settings tab within the IBERT Console. SP623 IBERT Getting Started Guide www.xilinx.com UG752 (v1.0.1) January 26, 2011...
  • Page 24 Note the line rate is 3.125 Gb/s for all four GTP transceivers (MGT Link Status in Figure 29). X-Ref Target - Figure 29 UG752_29_052610 Figure 29: GTP Transceiver Link Status www.xilinx.com SP623 IBERT Getting Started Guide UG752 (v1.0.1) January 26, 2011...
  • Page 25 Note the GTP transmitter differential output swing is preset to 595 mV (0011) as shown in Figure X-Ref Target - Figure 30 UG752_30_052510 Figure 30: GTP Transceiver TX Differential Output Swing SP623 IBERT Getting Started Guide www.xilinx.com UG752 (v1.0.1) January 26, 2011...
  • Page 26 Close the ChipScope Pro Analyzer tool. Note: Do not save changes to the project. Remove power to the SP623 board by placing SW1 in the OFF position. Remove the SMA cables from the SP623 board. www.xilinx.com SP623 IBERT Getting Started Guide...

  • Page 27: Frequency Table

    76.800 Generic 66.667 Generic 315.000 OBSAI 153.600 Generic 133.333 Generic 320.000 OBSAI 307.200 Generic 166.667 Generic 325.000 OBSAI 614.400 Generic 266.667 Generic 330.000 OC-48 19.440 Generic 333.333 Generic 335.000 SP623 IBERT Getting Started Guide www.xilinx.com UG752 (v1.0.1) January 26, 2011...

  • Page 28: References

    525.000 Generic 400.000 Generic 465.000 References UG029, ChipScope Pro Software and Cores User Guide UG751, SP623 Spartan-6 FPGA GTP Transceiver Characterization Board User Guide. HW-CLK-101-SCLK2 SuperClock-2 Module User Guide www.xilinx.com SP623 IBERT Getting Started Guide UG752 (v1.0.1) January 26, 2011...

  • Page 29: Warranty

    For any breach by Xilinx of this limited warranty, the exclusive remedy of Customer and the sole liability of Xilinx shall be, at the option of Xilinx, to replace or repair the affected products, or to refund to Customer the price of the affected products. The availability of replacement products is subject to product discontinuation policies at Xilinx.
  • Page 30 Warranty www.xilinx.com SP623 IBERT Getting Started Guide UG752 (v1.0.1) January 26, 2011...

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