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Master UCF Listing
TheAC701 board master user constraints file (UCF) template provides for designs
targeting the AC701 board. Net names in the constraints listed below correlate with net
names on the latest AC701 board schematic. Users must identify the appropriate pins and
replace the net names below with net names in the user RTL. See the Constraints Guide at:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_3/cgd.pdf
for more information.
Users can refer to the UCF files generated by tools such as Memory Interface Generator
(MIG) for memory interfaces and Base System Builder (BSB) for more detailed I/O
standards information required for each particular interface. The FMC HPC connector J30
is connected to a 2.5V V
customer-specific circuitry, the FMC bank I/O standards must be uniquely defined by each
customer.
AC701 Board UCF Listing
#NET
No Connect
NET
FMC1_HPC_HA02_P
NET
FMC1_HPC_HA02_N
NET
FMC1_HPC_HA03_P
NET
FMC1_HPC_HA03_N
NET
FMC1_HPC_HA04_P
NET
FMC1_HPC_HA04_N
NET
FMC1_HPC_HA05_P
NET
FMC1_HPC_HA05_N
NET
FMC1_HPC_HA06_P
NET
FMC1_HPC_HA06_N
NET
FMC1_HPC_HA07_P
NET
FMC1_HPC_HA07_N
NET
FMC1_HPC_HA08_P
NET
FMC1_HPC_HA08_N
NET
FMC1_HPC_HA09_P
NET
FMC1_HPC_HA09_N
NET
FMC1_HPC_HA10_P
NET
FMC1_HPC_HA10_N
NET
FMC1_HPC_HA11_P
NET
FMC1_HPC_HA11_N
NET
FMC1_HPC_HA01_CC_P
NET
FMC1_HPC_HA01_CC_N
NET
FMC1_HPC_HA17_CC_P
NET
FMC1_HPC_HA17_CC_N
NET
FMC1_HPC_HA00_CC_P
NET
FMC1_HPC_HA00_CC_N
NET
FMC1_HPC_HA12_P
NET
FMC1_HPC_HA12_N
NET
FMC1_HPC_HA13_P
NET
FMC1_HPC_HA13_N
NET
FMC1_HPC_HA14_P
NET
FMC1_HPC_HA14_N
NET
FMC1_HPC_HA15_P
NET
FMC1_HPC_HA15_N
NET
FMC1_HPC_HA16_P
NET
FMC1_HPC_HA16_N
NET
FMC1_HPC_HA18_P
NET
FMC1_HPC_HA18_N
AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
bank. Because each user's FMC card implements
cco
LOC = AB22 | IOSTANDARD=LVCMOS25; # Bank
LOC = AE25 | IOSTANDARD=LVCMOS25; # Bank
LOC = AE26 | IOSTANDARD=LVCMOS25; # Bank
LOC = AC22 | IOSTANDARD=LVCMOS25; # Bank
LOC = AC23 | IOSTANDARD=LVCMOS25; # Bank
LOC = AF24 | IOSTANDARD=LVCMOS25; # Bank
LOC = AF25 | IOSTANDARD=LVCMOS25; # Bank
LOC = AD25 | IOSTANDARD=LVCMOS25; # Bank
LOC = AD26 | IOSTANDARD=LVCMOS25; # Bank
LOC = AE23 | IOSTANDARD=LVCMOS25; # Bank
LOC = AF23 | IOSTANDARD=LVCMOS25; # Bank
LOC = AD23 | IOSTANDARD=LVCMOS25; # Bank
LOC = AD24 | IOSTANDARD=LVCMOS25; # Bank
LOC = AD21 | IOSTANDARD=LVCMOS25; # Bank
LOC = AE21 | IOSTANDARD=LVCMOS25; # Bank
LOC = AF19 | IOSTANDARD=LVCMOS25; # Bank
LOC = AF20 | IOSTANDARD=LVCMOS25; # Bank
LOC = AE22 | IOSTANDARD=LVCMOS25; # Bank
LOC = AF22 | IOSTANDARD=LVCMOS25; # Bank
LOC = AD20 | IOSTANDARD=LVCMOS25; # Bank
LOC = AE20 | IOSTANDARD=LVCMOS25; # Bank
LOC = AB21 | IOSTANDARD=LVCMOS25; # Bank
LOC = AC21 | IOSTANDARD=LVCMOS25; # Bank
LOC = AA20 | IOSTANDARD=LVCMOS25; # Bank
LOC = AB20 | IOSTANDARD=LVCMOS25; # Bank
LOC = AA19 | IOSTANDARD=LVCMOS25; # Bank
LOC = AB19 | IOSTANDARD=LVCMOS25; # Bank
LOC = AC19 | IOSTANDARD=LVCMOS25; # Bank
LOC = AD19 | IOSTANDARD=LVCMOS25; # Bank
LOC = AC18 | IOSTANDARD=LVCMOS25; # Bank
LOC = AD18 | IOSTANDARD=LVCMOS25; # Bank
LOC = AE18 | IOSTANDARD=LVCMOS25; # Bank
LOC = AF18 | IOSTANDARD=LVCMOS25; # Bank
LOC = Y18
| IOSTANDARD=LVCMOS25; # Bank
LOC = AA18 | IOSTANDARD=LVCMOS25; # Bank
LOC = AE17 | IOSTANDARD=LVCMOS25; # Bank
LOC = AF17 | IOSTANDARD=LVCMOS25; # Bank
LOC = AA17 | IOSTANDARD=LVCMOS25; # Bank
LOC = AB17 | IOSTANDARD=LVCMOS25; # Bank
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Appendix C
12 VCCO - VCCO_VADJ - IO_0_12
12 VCCO - VCCO_VADJ - IO_L1P_T0_12
12 VCCO - VCCO_VADJ - IO_L1N_T0_12
12 VCCO - VCCO_VADJ - IO_L2P_T0_12
12 VCCO - VCCO_VADJ - IO_L2N_T0_12
12 VCCO - VCCO_VADJ - IO_L3P_T0_DQS_12
12 VCCO - VCCO_VADJ - IO_L3N_T0_DQS_12
12 VCCO - VCCO_VADJ - IO_L4P_T0_12
12 VCCO - VCCO_VADJ - IO_L4N_T0_12
12 VCCO - VCCO_VADJ - IO_L5P_T0_12
12 VCCO - VCCO_VADJ - IO_L5N_T0_12
12 VCCO - VCCO_VADJ - IO_L6P_T0_12
12 VCCO - VCCO_VADJ - IO_L6N_T0_VREF_12
12 VCCO - VCCO_VADJ - IO_L7P_T1_12
12 VCCO - VCCO_VADJ - IO_L7N_T1_12
12 VCCO - VCCO_VADJ - IO_L8P_T1_12
12 VCCO - VCCO_VADJ - IO_L8N_T1_12
12 VCCO - VCCO_VADJ - IO_L9P_T1_DQS_12
12 VCCO - VCCO_VADJ - IO_L9N_T1_DQS_12
12 VCCO - VCCO_VADJ - IO_L10P_T1_12
12 VCCO - VCCO_VADJ - IO_L10N_T1_12
12 VCCO - VCCO_VADJ - IO_L11P_T1_SRCC_12
12 VCCO - VCCO_VADJ - IO_L11N_T1_SRCC_12
12 VCCO - VCCO_VADJ - IO_L12P_T1_MRCC_12
12 VCCO - VCCO_VADJ - IO_L12N_T1_MRCC_12
12 VCCO - VCCO_VADJ - IO_L13P_T2_MRCC_12
12 VCCO - VCCO_VADJ - IO_L13N_T2_MRCC_12
12 VCCO - VCCO_VADJ - IO_L14P_T2_SRCC_12
12 VCCO - VCCO_VADJ - IO_L14N_T2_SRCC_12
12 VCCO - VCCO_VADJ - IO_L15P_T2_DQS_12
12 VCCO - VCCO_VADJ - IO_L15N_T2_DQS_12
12 VCCO - VCCO_VADJ - IO_L16P_T2_12
12 VCCO - VCCO_VADJ - IO_L16N_T2_12
12 VCCO - VCCO_VADJ - IO_L17P_T2_12
12 VCCO - VCCO_VADJ - IO_L17N_T2_12
12 VCCO - VCCO_VADJ - IO_L18P_T2_12
12 VCCO - VCCO_VADJ - IO_L18N_T2_12
12 VCCO - VCCO_VADJ - IO_L19P_T3_12
12 VCCO - VCCO_VADJ - IO_L19N_T3_VREF_12
77
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