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Chapter 6: VGA Display Port
As shown in
sync (VS) timings signals and coordinates the delivery of video data on each pixel clock.
The pixel clock defines the time available to display one pixel of information. The VS signal
defines the refresh frequency of the display, or the frequency at which all information on the
display is redrawn. The minimum refresh frequency is a function of the display's phosphor
and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz
range. The number of horizontal lines displayed at a given refresh frequency defines the
horizontal retrace frequency.
VGA Signal Timing
The signal timings in
25 MHz pixel clock and 60 Hz ± 1 refresh.
the timing symbols. The timing for the sync pulse width (T
intervals (T
and back porch intervals are the pre- and post-sync pulse times. Information cannot be
displayed during these times.
Table 6-2: 640x480 Mode VGA Timing
Generally, a counter clocked by the pixel clock controls the horizontal timing. Decoded
counter values generate the HS signal. This counter tracks the current pixel display
location on a given row.
A separate counter tracks the vertical timing. The vertical-sync counter increments with
each HS pulse and decoded values generate the VS signal. This counter tracks the current
display row. These two continuously running counters form the address into a video
display buffer. For example, the on-board DDR SDRAM provides an ideal display buffer.
No time relationship is specified between the onset of the HS pulse and the onset of the VS
pulse. Consequently, the counters can be arranged to easily form video RAM addresses, or
to minimize decoding logic for sync pulse generation.
56
Figure
6-2, the VGA controller generates the horizontal sync (HS) and vertical
Table 6-2
and T
) are based on observations from various VGA displays. The front
FP
BP
Symbol
Parameter
T
Sync pulse time
S
T
Display time
DISP
T
Pulse width
PW
T
Front porch
FP
T
Back porch
BP
T
pw
www.xilinx.com
are derived for a 640-pixel by 480-row display using a
Figure 6-3
shows the relation between each of
Vertical Sync
Time
Clocks
16.7 ms
416,800
15.36 ms
384,000
64 µs
1,600
320 µs
8,000
928 µs
23,200
T
S
T
disp
Figure 6-3: VGA Control Timing
Spartan-3E Starter Kit Board User Guide
) and front and back porch
PW
Horizontal Sync
Lines
Time
Clocks
521
32 µs
480
25.6 µs
2
3.84 µs
10
640 ns
29
1.92 µs
T
fp
UG230_c6_03_021706
UG230 (v1.0) March 9, 2006
R
800
640
96
16
48
T
bp
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