Table of Contents
Advertisement
R
Additional Design Details
Figure 12-18
Starter Kit board. In most applications, this interface is as simple as that shown in
Figure
configuration options and demonstrates additional Spartan-3E capabilities.
SF_A<17>
(T16)
SF_A<18>
(U15)
SF_A<19>
(V15)
Figure 12-18: Additional SPI Flash Interface Design Details
Shared SPI Bus with Peripherals
After configuration, the SPI Flash configuration pins are available to the application. On
the Spartan-3E Starter Kit board, the SPI bus is shared by other SPI-capable peripheral
devices, as shown in
FPGA application must disable the other devices on the shared PCI bus.
the signal names and disable values for the other devices.
Table 12-3: Disable Other Devices on SPI Bus
DAC_CS
AMP_CS
AD_CONV
SF_CE0
FPGA_INIT_B
Spartan-3E Starter Kit Board User Guide
UG230 (v1.0) March 9, 2006
provides additional details of the SPI Flash interface used on the Spartan-3E
12-1. The Spartan-3E Starter Kit board, however, supports of variety of
Spartan-3E FPGA
MOSI/CSI_B
(T4)
DIN/D0
VS2/A17
(N10)
VS1/A18
CCLK
(U16)
VS0/A19
CSO_B
(U3)
User-I/O
(R12)
Programming
Figure
Signal
Digital-to-Analog Converter (DAC)
Programmable Pre-Amplifier
Analog-to-Digital Converter (ADC)
StrataFlash Parallel Flash PROM
Platform Flash PROM
www.xilinx.com
SPI_MOSI
SPI_MISO
SPI_SCK
SPI_SS_B
SPI_ALT_CS_JP11
Jumper J11
Header J12
12-18. To access the SPI Flash memory after configuration, the
Disabled Device
Additional Design Details
3.3V
STMicro M25P16
SPI Serial Flash
D
Q
C
W
S
HLD
DAC
AMP
ADC
Platform
Flash
Strata-
Flash
UG230_c15_17_030306
Table 12-3
shows
Disable Value
1
1
0
1
1
99
Advertisement
Table of Contents
