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Xilinx XtremeDSP Spartan-3A DSP Technical Reference Manual

By lyrtech
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Summary of Contents for Xilinx XtremeDSP Spartan-3A DSP

  • Page 2 Revision history Revision Date Comments June, 2007 Preliminary version. July, 2007 Added appendix 1. July, 2007 Updated version for final review. • Updated FMC information August, 2007 • Updated support information • Adjusted page numbering to meet specifications. • FPGA pinout for DDR2 inteface added •...
  • Page 3 MATLAB, Simulink, and Real-Time Workshop are registered trademarks of The MathWorks, Inc. Xilinx, Spartan, and Virtex are registered trademarks of Xilinx, Inc. Texas Instruments, Code Composer Studio, C62x, C64x, and C67x are trademarks of Texas Instruments Incorporated. All other product names are trademarks or registered trademarks of their respective holders.
  • Page 4 This page was left intentionally blank.

  • Page 5: Introduction

    Congratulations on the purchase of the XtremeDSP Spartan-3A DSP Development Board. Outstanding features and potential applications The XtremeDSP Spartan-3A DSP Development Board uses, as its name implies, the new Spartan-3A DSP series of FPGAs from the Xilinx XtremeDSP product line. These devices offer developers great flexibility, a wide range of peripherals, and a cost-efficient solution to accelerate the development of new products.

  • Page 6: Additional Support Resources

    Xilinx Web site and search the database of silicon and software questions and answers, or open a technical support case in WebCase at www.xilinx.com/support.

  • Page 7: Table Of Contents

    Maximum power consumption..........................33 FPGA .................................. 33 Memory ................................33 Connectors and interfaces ........................... 34 Known issues..........................35 Appendix 1 Clock generator programming................37 Installing the clock generator software........................ 37 Generating an SVF file............................37 Downloading to the XtremeDSP Spartan-3A DSP Development Board ............40...
  • Page 8 XtremeDSP Spartan-3A DSP Development Board - Technical reference guide - v1.1 This page was left intentionally blank.

  • Page 9: List Of Figures And Tables

    Figure 7 Detailed I/O configuration of the 5V9885....................38 Figure 8 Assigning the register settings........................39 Figure 9 Programming the XtremeDSP Spartan-3A DSP Development Board with iMPACT ......... 40 Table 1 FPGA USB/System ACE interface pinout..................... 13 Table 2 Ethernet PHY default configuration ......................14 Table 3 Soft Touch connector pin assignments ......................
  • Page 10 XtremeDSP Spartan-3A DSP Development Board - Technical reference guide - v1.1 This page was left intentionally blank.

  • Page 11: Hardware Overview

    Hardware overview Hardware overview This chapter presents an overview the XtremeDSP Spartan-3A DSP Development Board by describing its parts and functions. XtremeDSP Spartan-3A DSP Development Board block diagram The XtremeDSP Spartan-3A DSP Development Board can be represented by the following block diagram:...

  • Page 12: Xtremedsp Spartan-3A Dsp Development Board Parts And Functions

    XtremeDSP Spartan-3A DSP Development Board - Technical reference guide - v1.1 XtremeDSP Spartan-3A DSP Development Board parts and functions Physically, the XtremeDSP Spartan-3A DSP Development Board is laid out as follows: Figure 2 XtremeDSP Spartan-3A DSP Development Board top view 1.
  • Page 13 Board. 3. USB host port Type A connector. Used to connect a host device to the XtremeDSP Spartan-3A DSP Development Board. 4. AC’97 SoundaMAX codec Analog Devices AD1981B. The device supports 16-bit stereo audio and sampling rates up to 48 kHz. The sampling rate for recording and playback may also be different.
  • Page 14 Center positive, 2.1-mm × 5.5-mm barrel-type plug. Used to connect the supplied AC adaptor. 13. Power switch Allows you to turn the XtremeDSP Spartan-3A DSP Development Board on and off by controlling the 12-V supply of the board. 14. Soft Touch connector The Soft Touch connector (J12) allows you to monitor signals between the FPGA and the FMC expansion connector.
  • Page 15 Hardware overview Table 3 Soft Touch connector pin assignments Soft Touch pin FPGA pin Description Soft Touch pin FPGA pin Description FMC_LA18_P FMC_LA19_P FMC_LA18_N FMC_LA19_N FMC_LA31_P FMC_LA32_P FMC_LA31_N FMC_LA32_N FMC_LA29_P FMC_LA30_P FMC_LA29_N FMC_LA30_N FMC_LA16_P FMC_LA17_P FMC_LA16_N FMC_LA17_N FMC_LA14_P FMC_LA15_P FMC_LA14_N FMC_LA15_N FMC_LA12_P FMC_LA13_P...
  • Page 16 XtremeDSP Spartan-3A DSP Development Board - Technical reference guide - v1.1 Table 4 FMC expansion connector pin assignments (1) FMC pin FPGA pin Signal FMC pin FPGA pin Signal PGC2M DP0C2MP DP0C2MN GBTCLK0M2CP GBTCLK0M2CN DP0M2CP DP0M2CN LA28PCC LA28NCC LA29P LA29N...
  • Page 17 Hardware overview FMC pin FPGA pin Signal FMC pin FPGA pin Signal 12P0V 3P3V 3P3V 3P3V Table 5 FMC expansion connector pin assignments (2) FMC pin FPGA pin Signal FMC pin FPGA pin Signal VREFAM2C CLK0C2MP PRSNTM2CL CLK0C2MN CLK0M2CP CLK0M2CN LA17P LA17N LA06P...
  • Page 18 XtremeDSP Spartan-3A DSP Development Board - Technical reference guide - v1.1 FMC pin FPGA pin Signal FMC pin FPGA pin Signal LA14N LA26P LA26N LA15P LA15N LA27P LA27N LA16P LA16N VADJ VADJ 16. ZBT synchronous SRAM ISSI IS61NLP25636A-200TQL. The ZBT synchronous SRAM is high-speed, low-latency external memory for the FPGA.
  • Page 19 18. Power supply devices The power supply circuitry of the XtremeDSP Spartan-3A DSP Development Board generates 0.9 V, 1.2 V, 1.8 V, 2.5 V, 3.3 V, and 5 V, as well as one adjustable voltage to power the components of the board. The 1.2 V (PS3), 1.8 V (PS5), 2.5 V (PS2), 3.3 V (PS4), and adjustable (PS1) supplies are driven by Linear...
  • Page 20 XtremeDSP Spartan-3A DSP Development Board - Technical reference guide - v1.1 Table 7 FPGA I/O bank voltage rail FPGA bank I/O voltage rail Adjustable (2.5 V or 3.3 V) 1.8 V 3.3 V Adjustable (1.5 V, 1.8 V, 2.5 V, or 3.3 V) 21.
  • Page 21 The JTAG header (P5) allows programming devices and troubleshooting the FPGA. The JTAG port supports the Xilinx Parallel Cable III, Parallel Cable IV, or Platform USB cable products. Third-party configuration products might also be available. The JTAG chain can also be extended to the FMC expansion module when it is present.
  • Page 22 Button FPGA Pin Description PORESET 30. Configuration jumpers 10 configuration jumpers are present on the XtremeDSP Spartan-3A DSP Development Board. The following tables describes how to use them: Table 13 Configuration jumpers Jumper Function Prevents the USB controller from running the...
  • Page 23 Hardware overview 31. User-defined DIP switches Eight general-purpose, active-high DIP switches (S3) are connected to the user I/O pins of the FPGA. Table 14 User-defined DIP switch FPGA pin assignments Switch no. FPGA pin Description FPGA_DIP_SW0 FPGA_DIP_SW1 FPGA_DIP_SW2 FPGA_DIP_SW3 FPGA_DIP_SW4 FPGA_DIP_SW5 FPGA_DIP_SW6 FPGA_DIP_SW7...
  • Page 24 CONFIG FROM XCF32P FLASH 34. CPLD Xilinx XC2C64A CoolRunner-II. This device is designed for high-performance and low-power applications. The CPLD is used to configure the XtremeDSP Spartan-3A DSP Development Board and to provide statuses through the status LEDs (below). 35. Status LEDs The status LEDs are driven by the CPLD to provide statuses on the XtremeDSP Spartan-3A DSP Development Board.
  • Page 25 Hardware overview 36. Audio input output connectors Microphone, line in, line out, and headphones connectors. All the connectors are stereo except the microphone connector. Table 19 Audio connectors Connector Function Microphone — In Analog line — In Analog line — Out Headphones —...

  • Page 26: Bottom

    • Only half the the available memory of the DDR2 SDRAM (i.e. 256 MB) is available because of certain limitations. • The XtremeDSP Spartan-3A DSP Development Board is only tested for DDR2 SDRAM operation at a data rate of 266 MHz (133 MHz clock rate). Using faster data rates is possible, but untested and not...
  • Page 27 Hardware overview Table 20 FPGA DDR2 interface pinout FPGA pin Description FPGA pin Description AA25 DDR2_A_0 DDR2_0_DQ_0 AA22 DDR2_A_1 DDR2_0_DQ_1 AB26 DDR2_A_2 DDR2_0_DQ_2 DDR2_A_3 DDR2_0_DQ_3 AC24 DDR2_A_4 DDR2_0_DQ_4 AA24 DDR2_A_5 DDR2_0_DQ_5 AD26 DDR2_A_6 DDR2_0_DQ_6 AE26 DDR2_A_7 DDR2_0_DQ_7 AB23 DDR2_A_8 DDR2_0_DQ_8 AC25 DDR2_A_9 DDR2_0_DQ_9...
  • Page 28 XtremeDSP Spartan-3A DSP Development Board - Technical reference guide - v1.1 3. System ACE controller The Xilinx System ACE controller allows a type I CompactFlash card to program the FPGA through the JTAG port. The System ACEc controller supports up to eight configuration images on a single CompactFlash card.

  • Page 29: Fmc Expansion Connector

    The FMC expansion connector (J13) follows the VITA 57.1 FMC standard (standard to be released at a later date) and it is used in low-pin-count (LPC) format. The XtremeDSP Spartan-3A DSP Development Board was designed with a preliminary version of the standard.

  • Page 30: Ddr2 Memory

    MIG compatibility Since MIG doesn’t directly generate compatible design for the XtremeDSP Spartan-3A DSP Development Board at this time, the used design can’t be called MIG-compatible. However, the board can be used with a modified design from MIG.

  • Page 31: Configuration Options

    Configuration options Configuration options The FPGA of the XtremeDSP Spartan-3A DSP Development Board can be configured by four major devices: • Xilinx download cable (JTAG) • System ACE controller (JTAG) • Board flash memory • SPI flash memory The following section provides an overview of the possible ways the FPGA can be configured.

  • Page 32: Board Flash Memory Configuration

    (see item 33, above). When correctly configured, the board flash memory programs the FPGA when the XtremeDSP Spartan-3A DSP Development Board is turned on or whenever the program button is depressed (see item 22, above).

  • Page 33: Specifications

    Specifications Specifications This chapter outlines the technical specifications of the XtremeDSP Spartan-3A DSP Development Board. Note The specifications in this chapter are subject to change without notice. General specifications • Mass: 359.1 g • Length: 254.0 mm • Width: 165.1 mm •...

  • Page 34: Connectors And Interfaces

    XtremeDSP Spartan-3A DSP Development Board - Technical reference guide - v1.1 Connectors and interfaces • RJ45 — 10Base-T, 100Base-TX, 1000Base-T Ethernet • RS232 serial port • System ACE Compact Flash • JTAG programming interface • Video (DVI/VGA) output • Audio in (2×) — line and microphone •...

  • Page 35: Known Issues

    LA17 and LA28 are not connected to clock-capable I/Os. Recommendation 11 CLK0_M2C signals are not connected to dedicated clock pins. • The DDR2 interface performance is limited to a clock rate of 133 MHz on the XtremeDSP Spartan-3A DSP Development Board.
  • Page 36 XtremeDSP Spartan-3A DSP Development Board - Technical reference guide - v1.1 This page was left intentionally blank.

  • Page 37: Appendix 1 Clock Generator Programming

    EEPROM programmable clock generator that allows you to program the board’s clocks. This appendix explains how to use the IDT software to generate a combination of clock frequencies and implement them onto the XtremeDSP Spartan-3A DSP Development Board with a Xilinx download cable and JTAG flying wires. Installing the clock generator software 1.
  • Page 38 3. In the Input Clock Configurations group, select the Crystal Input Enable check box. 4. In the Output OUTx Control group, clear the /Out5 Invert check box. On the XtremeDSP Spartan-3A DSP Development Board, clock output 5 is usually used as a differential clock.
  • Page 39 0xB, then to copy the settings from register 0xC to register 0xF, and so on. Figure 8 presents how the contents are copied for registers 0x13, 0x17, 0x1B, and 0x21. Table 23 Register configuration Register address Register address (Config 0) (XtremeDSP Spartan-3A DSP Development Board configuration) 0x10 0x13 0x14 0x17 0x18 0x1B 0x20...

  • Page 40: Downloading To The Xtremedsp Spartan-3A Dsp Development Board

    7. Right-click the device and click Execute XSVF/SVF on the shortcut menu that appears. Figure 9 Programming the XtremeDSP Spartan-3A DSP Development Board with iMPACT 8. To complete programming the device, turn off the XtremeDSP Spartan-3A DSP Development Board, and then turn it on again.
  • Page 41 Appendix 1 Clock generator programming This page was left intentionally blank.

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