Connectorless Debugging Port Landing Pads (J6) - Xilinx Spartan-3E User Manual

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Connectorless Debugging Port Landing Pads (J6)

Landing pads for a connectorless debugging port are provided as header J6, shown in
Figure 15-1, page
probe, such as those available from Agilent, provides an interface to a logic analyzer. This
debugging port is intended primarily for the Xilinx ChipScope Pro software with the
Agilent's FPGA Dynamic Probe. It can, however, be used with either the Agilent or
Tektronix probes, without the ChipScope software, using FPGA Editor's probe command.
Refer to
probes, and connectors.
Table 15-3
remaining connector pads are unconnected. All 18 FPGA pins are shared with the FX2
connector (J3) and the 6-pin accessory port connectors (J1, J2, and J4). See
page 115
Table 15-3: Connectorless Debugging Port Landing Pads (J6)
Spartan-3E Starter Kit Board User Guide
UG230 (v1.0) March 9, 2006
113. There is no physical connector on the board. Instead a connectorless
"Related Resources," page 124
provides the connector pinout. Only 18 FPGA pins attach to the connector; the
for more information on how these pins are shared.
Signal Name FPGA Pin
FX2_IO1 B4
FX2_IO2 A4
GND GND
FX2_IO5 A6
FX2_IO6 B6
GND GND
FX2_IO9 D7
FX2_IO10 C7
GND GND
FX2_IO13 F9
FX2_IO14 E9
GND GND
FX2_IO17 F11
FX2_IO18 E11
www.xilinx.com
Connectorless Debugging Port Landing Pads (J6)
for more information on the ChipScope Pro tool,
Connectorless
Landing Pads FPGA Pin
A1 B1
A2 B2
A3 B3
A4 B4
A5 B5
A6 B6
A7 B7
A8 B8
A9 B9
A10 B10
A11 B11
A12 B12
A13 B13
A14 B14
A15 B15
A16 B16
A17 B17
A18 B18
A19 B19
A20 B20
A21 B21
A22 B22
A23 B23
A24 B24
A25 B25
A26 B26
A27 B27
Table 15-1,
Signal Name
GND GND
D5 FX2_IO3
C5 FX2_IO4
GND GND
E7 FX2_IO7
F7 FX2_IO8
GND GND
F8 FX2_IO11
E8 FX2_IO12
GND GND
D11 FX2_IO15
C11 FX2_IO16
GND GND
123