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Xilinx SP305 Spartan-3 User Manual

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SP305 Spartan-3
Development Platform
User Guide
UG216 (v1.1) March 3, 2006
UG216 (v1.1) March 3, 2006
SP305 Spartan-3 Development Platform User Guide
www.xilinx.com

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  • Page 1 SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006 UG216 (v1.1) March 3, 2006 SP305 Spartan-3 Development Platform User Guide www.xilinx.com...
  • Page 2 Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.
  • Page 3 Revision History SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006 The following table shows the revision history for this document.. Version Revision 11/23/05 Initial Xilinx release. In USB Controller with Host and Peripheral Ports (25) section, added note indicating 3/3/06 non-support for 2nd USB feature.
  • Page 4 SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006 www.xilinx.com...

  • Page 5: Table Of Contents

    Online Document ............2 SP305 Spartan-3 Development Platform User Guide Introduction .
  • Page 6 ........... . . 36 UG216 (v1.1) March 3, 2006 SP305 Spartan-3 Development Platform User Guide www.xilinx.com...

  • Page 7: About This Guide

    Guide Contents About This Guide The Xilinx Development Platform allows designers to investigate and experiment with features of the Spartan™-3 family of Xilinx FPGAs. This document describes features and operation of the SP305 Development Platform. Guide Contents This manual contains the following chapter: •...

  • Page 8: Online Document

    Figure 2-5 in the Virtex-II Red text location in another document Handbook. Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest speed files. www.xilinx.com SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006...

  • Page 9: Sp305 Spartan-3 Development Platform User Guide

    CAN and SPI interface ports • IFF one wire encryption device • Xilinx XCF32P Platform Flash configuration storage device • JTAG configuration port for use with Parallel Cable III or Parallel Cable IV cable SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006...

  • Page 10: Package Contents

    If the user purchased part number DO-SP305-DVLP-US (UE,UK) • SP305 Board • 5 Volt Power Supply • Full version of the Xilinx ISE and EDK development tools (1 year time-based license) • USB Download and Debug Cable • RS232 Null Modem Cable •...

  • Page 11: Block Diagram

    To FPGA Core 3.3 V TPS54310 3A SWIFT To FPGA I/O Digital Supply 1.8 V TPS54310 To PROM 150mA LDO ug216_01_101105 Figure 2-1: Spartan-3 SP-305 Development Platform Block Diagram SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006 www.xilinx.com...

  • Page 12: Detailed Description

    SP305 Spartan-3 Development Platform User Guide Detailed Description The SP305 Development Platform is shown in Figure 2-2 (front) and Figure 2-3 (back). The features/components on the board are identified by numbered yellow balloons. These features/components are then detailed or described in respectively numbered sections in the subsequent sections of this document.

  • Page 13: Spartan-3 Fpga (1)

    Figure 2-3: SP305 Development Platform (back view) Spartan-3 FPGA (1) A Xilinx XC3S1500-FG676-10 FPGA is installed on the development platform (the board). The FPGA is identified as component (1) in the heading above. The other features/components are numbered accordingly in the subsequent sections.

  • Page 14: Ac Adapter And Input Power Switch/Jack (2)

    SP305 Spartan-3 Development Platform User Guide I/O Voltage Rails The FPGA has 7 banks. The I/O voltage applied to each bank is summarized in Table 2-1. Table 2-1: I/O Voltage Rail of FPGA Banks FPGA Bank I/O Voltage Rail 3.3V 2.5V...

  • Page 15: Oscillator Sockets (5)

    There are eight general purpose (active-high) DIP switches connected to the user I/O pins of the FPGA. See Table 2-3 for a summary of these connections. Table 2-3: DIP Switches Connections (SW1) FPGA Pin FPGA Pin SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006 www.xilinx.com...

  • Page 16: User Leds (7)

    SP305 Spartan-3 Development Platform User Guide User LEDs (7) There are 4 green LEDs are general purpose LEDs arranged in a row. The LEDs are active high LEDs directly controllable by the FPGA: Table 2-4 summarizes the LED definitions and connections...

  • Page 17: Cpu Reset Button (10)

    The JTAG configuration port for the board (J20) allows for device programming and FPGA debug. The JTAG port supports the Xilinx Parallel Cable III or Parallel Cable IV products. Third-party configuration products may also be available. The JTAG chain may also be extended to an expansion board by setting jumper J26 accordingly.

  • Page 18: Configuration Address And Mode Dip Switches (13)

    SP305 Spartan-3 Development Platform User Guide The FPGA and Platform Flash memory can be configured through the JTAG port. The JTAG chain of the board is illustrated in Figure 2-5. PlatFlash FPGA Expansion ug216_05_101105 Figure 2-5: JTAG Chain The chain starts at the PC4 connector and goes through the Platform Flash memory, the FPGA, and an optional extension of the chain to the expansion card.

  • Page 19: Platform Flash Memory (15)

    There are 2 red LEDs are intended to be used for signaling error conditions such as bus errors, but can be used for any other purpose. They are active high LEDs directly controllable by the FPGA: SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006 www.xilinx.com...

  • Page 20: Rs-232 Serial Port 1 (20)

    SP305 Spartan-3 Development Platform User Guide Table 2-9 summarizes the Error LED definitions and connections Table 2-9: User and Error LED Connections Reference Label/Definition Color FPGA Pin Designator DS205 Error 1 AB11 DS206 Error 2 RS-232 Serial Port 1 (20) The SP-305 board contains two male DB-9 RS-232 serial port to enable the FPGA to communicate with serial data devices.

  • Page 21: Spi (22)

    (NO) push button, where rot_enc_s1 and rot_enc_s2 are floating connections to the FPGA. It is recommended that either a pull up or pull down are configured on these FPGA I/O. SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006...

  • Page 22: Usb Controller With Host And Peripheral Ports (25)

    SP305 Spartan-3 Development Platform User Guide Table 2-14: ROT ENC Pin Connections Label DESCRIPTION FPGA Pin ROT_ENC_A Channel A ROT_ENC_B Channel B ROT_ENC_S1 Pole 1 of NO switch ROT_ENC_S2 pole 2 of NO switch USB Controller with Host and Peripheral Ports (25) A Cypress CY7C67300 embedded USB host controller provides the USB connectivity for the board.

  • Page 23: 10/100 Smsc Ethernet Mac/Phy (26)

    ENET_SD7 Ethernet Data 7 ENET_SD8 Ethernet Data 8 ENET_SD9 Ethernet Data 9 ENET_SD10 Ethernet Data 10 ENET_SD11 Ethernet Data 11 ENET_SD12 Ethernet Data 12 ENET_SD13 Ethernet Data 13 SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006 www.xilinx.com...
  • Page 24 SP305 Spartan-3 Development Platform User Guide Table 2-16: 10/100 SMSC Ethernet MAC Clock Signals to PHY (Continued) Label FPGA Pin Description ENET_SD14 Ethernet Data 14 ENET_SD15 Ethernet Data 15 ENET_SD16 -SD31 Not Connected Ethernet Data 16 -31 ENET_AEN Address Enable...

  • Page 25: 10/100 Intel Ethernet Phy (27)

    PHY. The PHY is configured to default at power-on or reset. Table 2-17: 10/100 Intel Ethernet Clock Signals to PHY Label FPGA Pin Description PHY_TXD0 PHY_TXD1 PHY_TXD2 PHY_TXD3 PHY_TX_EN PHY_TX_ER SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006 www.xilinx.com...

  • Page 26: A/D Converter (Ad7928) (28)

    SP305 Spartan-3 Development Platform User Guide Table 2-17: 10/100 Intel Ethernet Clock Signals to PHY Label FPGA Pin Description PHY_RXD0 PHY_RXD1 PHY_RXD2 PHY_RXD3 PHY_RX_DV PHY_RX_ER PHY_MDINT PHY_MDIO PHY_CRS PHY_MDC PHY_SLW0 PHY_SLW1 PHY_RESET PHY_COL A/D Converter (AD7928) (28) There are eight ADC input signals. For more information see the board schematic and data sheet for the AD7928 ADC device.

  • Page 27: Vga Output (30)

    IIC SDA and IIC SCL through a Zero ohm resistors R159 and R160. Table 2-21: VGA FPGA Pins Label FPGA Pin Description VGA_B0 4.7K to GND VGA_B1 4.7K to GND VGA_B2 4.7K to GND VGA_B3 Blue 3 SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006 www.xilinx.com...

  • Page 28: Differential Clock Input And Output With Sma Connectors (31)

    SP305 Spartan-3 Development Platform User Guide Table 2-21: VGA FPGA Pins Label FPGA Pin Description VGA_B4 Blue 4 VGA_B5 Blue 5 VGA_B6 Blue 6 VGA_B7 Blue 7 VGA_R0 4.7K to GND VGA_R1 4.7K to GND VGA_R2 4.7K to GND VGA_R3...

  • Page 29: Expansion Headers (32)

    J5, Pin 34 HDR2_34 J5, Pin 36 HDR2_36 J5, Pin 38 HDR2_38 AA22 J5, Pin 40 AA21 HDR2_40 J5, Pin 42 HDR2_42 AB24 J5, Pin 44 AB23 HDR2_44 SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006 www.xilinx.com...
  • Page 30 SP305 Spartan-3 Development Platform User Guide Table 2-23: Expansion I/O Differential Connections (J5) (Continued) Header Pin Label FPGA Pin Header Pin FPGA Pin Label (Diff Pair (Diff Pair (Diff Pair (Diff Pair (Diff Pair (Diff Pair Neg) Neg) Neg) Pos)
  • Page 31 The SP-305 expansion connector is backward compatible with the expansion connectors on the ML320, ML321, and ML323 boards, thereby allowing their daughter cards to be used with the SP-305 Development Platform. Table 2-25 summarizes the additional expansion I/O connections. SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006 www.xilinx.com...
  • Page 32 SP305 Spartan-3 Development Platform User Guide Table 2-25: Additional Expansion I/O Connections Header Pin Label FPGA Pin Description J3, Pin 1 VCC5 5V Power Supply J3, Pin 2 VCC5 5V Power Supply J3, Pin 3 VCC5 5V Power Supply J3, Pin 4...

  • Page 33: Ps/2 Mouse And Keyboard Ports (33)

    2,3 it is connected the FPGA I/O for the CAN RX and TX. Table 2-27: MPC 2551 MAC Connections Reference Label/Definition FPGA Pin Designator FPGA_CAN_RXCAN FPGA_CAN_TXCAN SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006 www.xilinx.com...
  • Page 34 SP305 Spartan-3 Development Platform User Guide Table 2-27: MPC 2551 MAC Connections Reference Label/Definition FPGA Pin Designator CAN_CLK CAN_SOF CAN_TX0RTS CAN_TX1RTS CAN_TX2RTS CAN_CS CAN_SO CAN_SI CAN_SCK CAN_INT CAN_RESET CAN_RX0BF CAN_RX1BF Selecting an FPGA CAN MAC or the CAN MPC2551 MAC device (35b) The Jumper J35 will select between the FPGA_CAN_TXCAN and the CAN_TXCAN_MAC.

  • Page 35: Ddr Sdram (36)

    Spartan-3 DCMs. The board is designed so that the DDR clock signal reaches the FPGA clock feedback pin at the same time as it arrives at the DDR chips. SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006...

  • Page 36: Zbt Synchronous Sram (37)

    SP305 Spartan-3 Development Platform User Guide DDR Loop Signal The DDR loop signal is a trace driven and then received back at the FPGA with a delay equal to the sum of the trace delays of the clock and DQS signals. This looped trace can be used in high-speed memory controllers to help compensate for the physical trace delays between the FPGA and DDR chips.
  • Page 37 AD17 SRAM_FLASH_A7 AD18 SRAM_FLASH_A8 AE18 SRAM_FLASH_A9 SRAM_FLASH_A10 AC17 SRAM_FLASH_A11 SRAM_FLASH_A12 AA14 SRAM_FLASH_A13 SRAM_FLASH_A14 AB15 SRAM_FLASH_A15 AD15 SRAM_FLASH_A16 AF17 SRAM_FLASH_A17 SRAM_FLASH_A18 AA16 SRAM_FLASH_A19 AB17 SRAM_FLASH_A20 SRAM_FLASH_A21 AC10 SRAM_FLASH_A22 AB10 SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006 www.xilinx.com...

  • Page 38: Linear Flash Memory Chips (38)

    SP305 Spartan-3 Development Platform User Guide Table 2-29: SRAM (Continued) Label FPGA Pin Description SRAM_BW0 AF16 SRAM_BW1 AE16 SRAM_BW2 AA15 SRAM_BW3 SRAM_AVD_LD_N SRAM_CE1_N AC11 SRAM_FLASH_WE_N SRAM_OE_N AF10 SRAM_ZZ AE10 SRAM_MODE AD10 SRAM_DQP0 SRAM_DQP1 SRAM_DQP2 SRAM_DQP3 SRAM_CLK AF13 SRAM_CLK AF14 FEEDBACK...
  • Page 39 AE19 SRAM_FLASH_D27 AF19 SRAM_FLASH_D28 SRAM_FLASH_D29 AA18 SRAM_FLASH_D30 AB18 SRAM_FLASH_D31 AC18 FLASH_A0 AA10 Connected to Flash A0 SRAM_FLASH_A0 AE15 Connected to Flash A1 SRAM_FLASH_A1 AF15 SRAM_FLASH_A2 AB16 SRAM_FLASH_A3 AC16 SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006 www.xilinx.com...
  • Page 40 SP305 Spartan-3 Development Platform User Guide Table 2-30: Flash Label FPGA Pin Description SRAM_FLASH_A4 AE17 SRAM_FLASH_A5 AA17 SRAM_FLASH_A6 AD17 SRAM_FLASH_A7 AD18 SRAM_FLASH_A8 AE18 SRAM_FLASH_A9 SRAM_FLASH_A10 AC17 SRAM_FLASH_A11 SRAM_FLASH_A12 AA14 SRAM_FLASH_A13 SRAM_FLASH_A14 AB15 SRAM_FLASH_A15 AD15 SRAM_FLASH_A16 AF17 SRAM_FLASH_A17 SRAM_FLASH_A18 AA16 SRAM_FLASH_A19...

  • Page 41: Expansion Jtag Jumper (39)

    Bidirectional level shifting transistors allow the expansion card to utilize 2.5V to 5V signaling on IIC. Table 2-33: IIC FPGA Pins Label FPGA Pin Description IIC_SCL IIC clock IIC_SDA IIC Data SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006 www.xilinx.com...

  • Page 42: Iff (42)

    SP305 Spartan-3 Development Platform User Guide IFF (42) The SP-305 board has an IFF Encryption device connected to an FPGA I/O pin. This IFF device can be interfaced to an FPGA design in such a way that the functionality of the design can be licensed or enabled by the authentication with the IFF device.
  • Page 43 Connects Auxiliary Power to USB Port J32 2,3 Selects between the USB Debug UART port and the UART1 SOUT J33 2,3 Selects between the USB Debug UART port and the UART1 SIN SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006 www.xilinx.com...

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