R
Control
Figure 11-4
I/O pin assignment and the I/O standard used.
Setting the FPGA Mode Select Pins
Set the FPGA configuration mode pins for either BPI Up or BPI down mode, as shown in
Table
Table 11-4: Selecting BPI-Up or BPI-Down Configuration Modes (Header J30 in
Figure
Configuration
BPI Up
BPI Down
Related Resources
•
•
Spartan-3E Starter Kit Board User Guide
UG230 (v1.0) March 9, 2006
provides the UCF constraints for the StrataFlash control pins, including the
NET
"SF_BYTE"
LOC
= "C17" |
NET
"SF_CE0"
LOC
= "D16" |
NET
"SF_OE"
LOC
= "C18" |
NET
"SF_STS"
LOC
= "B18" |
NET
"SF_WE"
LOC
= "D17" |
Figure 11-4: UCF Location Constraints for StrataFlash Control Pins
11-4. See
4-2)
Mode Pins
Mode
M2:M1:M0
0:1:0
0:1:1
Intel J3 StrataFlash Data Sheet
http://www.intel.com/design/flcomp/products/j3/techdocs.htm#datasheets
Application Note 827, Intel StrataFlash
Design Guide
http://www.intel.com/design/flcomp/applnots/307257.htm
www.xilinx.com
Setting the FPGA Mode Select Pins
IOSTANDARD
= LVCMOS33 |
IOSTANDARD
= LVCMOS33 |
IOSTANDARD
= LVCMOS33 |
IOSTANDARD
= LVCMOS33 |
IOSTANDARD
= LVCMOS33 |
FPGA Configuration Image in
StrataFlash
FPGA starts at address 0 and
increments through address space.
The CPLD controls address lines
A[24:20] during BPI configuration.
FPGA starts at address 0xFF_FFFF
and decrements through address
space. The CPLD controls address
lines A[24:20] during BPI
configuration.
®
Memory (J3) to Xilinx Spartan-3E FPGA
DRIVE
= 4 |
SLEW
= SLOW ;
DRIVE
= 4 |
SLEW
= SLOW ;
DRIVE
= 4 |
SLEW
= SLOW ;
DRIVE
= 4 |
SLEW
= SLOW ;
DRIVE
= 4 |
SLEW
= SLOW ;
Jumper Settings
M0
M1
M2
J30
M0
M1
M2
J30
87