Ucf Location Constraints; Fpga Connections To Cpld; Cpld - Xilinx Spartan-3E User Manual

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UCF Location Constraints

There are two sets of constraints listed below
XC2C64A CoolRunner-II CPLD.

FPGA Connections to CPLD

Figure 16-2
including the I/O pin assignment and the I/O standard used.

CPLD

Figure 16-3
and the I/O standard used.
Spartan-3E Starter Kit Board User Guide
UG230 (v1.0) March 9, 2006
provides the UCF constraints for the FPGA connections to the CPLD ,
NET "XC_CMD<1>" LOC = "N18" |
NET "XC_CMD<0>" LOC = "P18" |
NET "XC_D<2>" LOC = "F17" |
NET "XC_D<1>" LOC = "F18" |
NET "XC_D<0>" LOC = "G16" |
NET "FPGA_M2" LOC = "T10" |
NET "FPGA_M1" LOC = "V11" |
NET "FPGA_M0" LOC = "M10" |
NET "XC_CPLD_EN" LOC = "B10" |
NET "XC_TRIG" LOC = "R17" |
NET "XC_GCK0" LOC = "H16" |
NET "GCLK10" LOC = "C9"
NET "SPI_SCK" LOC = "U16" |
# SF_A<24> is the same as FX2_IO<32>
NET "SF_A<24>" LOC = "A11" |
NET "SF_A<23>" LOC = "N11" |
NET "SF_A<22>" LOC = "V12" |
NET "SF_A<21>" LOC = "V13" |
NET "SF_A<20>" LOC = "T12" |
Figure 16-2: UCF Location Constraints for FPGA Connections to CPLD
provides the UCF constraints for the CPLD , including the I/O pin assignment
NET "XC_WDT_EN" LOC = "P16" |
NET "XC_CMD<1>" LOC = "P30" |
NET "XC_CMD<0>" LOC = "P29" |
NET "XC_D<2>" LOC = "P36" |
NET "XC_D<1>" LOC = "P34" |
NET "XC_D<0>" LOC = "P33" |
NET "FPGA_M2" LOC = "P8"
NET "FPGA_M1" LOC = "P6"
NET "FPGA_M0" LOC = "P5"
NET "XC_CPLD_EN" LOC = "P42" |
NET "XC_TRIG" LOC = "P41" |
NET "XC_DONE" LOC = "P40" |
NET "XC_PROG_B" LOC = "P39" |
NET "XC_GCK0" LOC = "P43" |
NET "GCLK10" LOC = "P1"
NET "SPI_SCK" LOC = "P44" |
# SF_A<24> is the same as FX2_IO<32>
NET "SF_A<24>" LOC = "P23" |
NET "SF_A<23>" LOC = "P22" |
NET "SF_A<22>" LOC = "P21" |
NET "SF_A<21>" LOC = "P20" |
NET "SF_A<20>" LOC = "P19" |
Figure 16-3: UCF Location Constraints for the XC2C64A CPLD
www.xilinx.com
–
one for the Spartan-3E FPGA and one for the
IOSTANDARD = LVCMOS33
IOSTANDARD = LVCMOS33
IOSTANDARD = LVCMOS33
IOSTANDARD = LVCMOS33
IOSTANDARD = LVCMOS33
IOSTANDARD = LVCMOS33
IOSTANDARD = LVCMOS33
IOSTANDARD = LVCMOS33
IOSTANDARD = LVCMOS33
IOSTANDARD = LVCMOS33 ;
IOSTANDARD = LVCMOS33
| IOSTANDARD = LVCMOS33
IOSTANDARD = LVCMOS33
IOSTANDARD = LVCMOS33
IOSTANDARD = LVCMOS33
IOSTANDARD = LVCMOS33
IOSTANDARD = LVCMOS33
IOSTANDARD = LVCMOS33
IOSTANDARD = LVCMOS33 ;
IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 |
| IOSTANDARD = LVCMOS33 |
| IOSTANDARD = LVCMOS33 |
| IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 |
| IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 |
IOSTANDARD = LVCMOS33 |
UCF Location Constraints
| DRIVE = 4 | SLEW = SLOW ;
| DRIVE = 4 | SLEW = SLOW ;
| DRIVE = 4 | SLEW = SLOW ;
| DRIVE = 4 | SLEW = SLOW ;
| DRIVE = 4 | SLEW = SLOW ;
| DRIVE = 4 | SLEW = SLOW ;
| DRIVE = 4 | SLEW = SLOW ;
| DRIVE = 4 | SLEW = SLOW ;
| DRIVE = 4 | SLEW = SLOW ;
| DRIVE = 4 | SLEW = SLOW ;
| DRIVE = 4 | SLEW = SLOW ;
| DRIVE = 4 | SLEW = SLOW ;
| DRIVE = 4 | SLEW = SLOW ;
| DRIVE = 4 | SLEW = SLOW ;
| DRIVE = 4 | SLEW = SLOW ;
| DRIVE = 4 | SLEW = SLOW ;
| DRIVE = 4 | SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
SLEW = SLOW ;
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