Ucf Location Constraints; Analog To Digital Converter (Adc); Interface; Spi Control Interface - Xilinx Spartan-3E User Manual

Starter kit board
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R
The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency.

UCF Location Constraints

Figure 10-5
including the I/O pin assignment and I/O standard used.

Analog to Digital Converter (ADC)

The LTC1407A-1 provides two ADCs. Both analog inputs are sampled simultaneously
when the AD_CONV signal is applied.

Interface

Table 10-3
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The
DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is
the active-Low, asynchronous reset input to the DAC.
Table 10-3: ADC Interface Signals
SPI_SCK
AD_CONV
SPI_MISO

SPI Control Interface

Figure 10-6
When the AD_CONV signal goes High, the ADC simultaneously samples both analog
channels. The results of this conversion are not presented until the next time AD_CONV is
asserted, a latency of one sample. The maxim sample rate is approximately 1.5 MHz.
The ADC presents the digital representation of the sampled analog values as a 14-bit, two's
complement binary value.
Spartan-3E Starter Kit Board User Guide
UG230 (v1.0) March 9, 2006
provides the User Constraint File (UCF) constraints for the amplifier interface,
NET
"SPI_MOSI"
LOC
= "T4"
NET
"AMP_CS"
LOC
= "N7"
NET
"SPI_SCK"
LOC
= "U16" |
NET
"AMP_SHDN"
LOC
= "P7"
NET
"AMP_DOUT"
LOC
= "E18" |
Figure 10-5: UCF Location Constraints for the DAC Interface
lists the interface signals between the FPGA and the ADC. The SPI_MOSI,
Signal
FPGA Pin
Direction
U16
FPGA ADC Clock
P11
FPGA ADC Active-High shutdown and reset.
N10
FPGA ADC Serial data: Master Input, Serial Output. Presents
provides an example SPI bus transaction to the ADC.
www.xilinx.com
Analog to Digital Converter (ADC)
|
IOSTANDARD
= LVCMOS33 |
|
IOSTANDARD
= LVCMOS33 |
IOSTANDARD
= LVCMOS33 |
|
IOSTANDARD
= LVCMOS33 |
IOSTANDARD
= LVCMOS33 ;
Description
the digital representation of the sample analog
values as two 14-bit two's complement binary
values.
SLEW
= SLOW |
DRIVE
= 6 ;
SLEW
= SLOW |
DRIVE
= 6 ;
SLEW
= SLOW |
DRIVE
= 8 ;
SLEW
= SLOW |
DRIVE
= 6 ;
77

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