Insert Jumper On Jp8 And Hold Prog_B Low - Xilinx Spartan-3E User Manual

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Table 12-2: Cable Connections to J12 Header
J12 Header Label
JTAG3 Cable Label
Flying Leads Label

Insert Jumper on JP8 and Hold PROG_B Low

The JTAG parallel programming cable directly accesses the SPI Flash pins. To avoid signal
contention with the FPGA, ensure that the connecting FPGA pins are high-impedance.
Force the FPGA's PROG_B pin Low by installing a jumper on JP8, next to the PROG push
button, as shown in
surrounding landmarks.
a) No Jumper: FPGA Operational (default)
Re-apply power to the Spartan-3E Starter Kit board.
Spartan-3E Starter Kit Board User Guide
UG230 (v1.0) March 9, 2006
a) JTAG3 Parallel Connector
Figure 12-15: Attaching a JTAG Parallel Programming Cable to the Board
Cable and Labels
Figure 12-16. See
JP8
PROG
GND
PROG
Figure 12-16: Installing the JP8 Jumper Holds the FPGA in Configuration State
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b) Parallel Cable III or Parallel Cable IV
with Flying Leads
Connections
SEL SDI SDO
TMS TDI TDO
TMS/ TDI/ TDO/
PROG DIN DONE
Figure 12-3, page 90
PROG
GND
b) Jumper Installed: FPGA Held in
Configuration State, I/Os in High Impedance
Configuring from SPI Flash
UG230_c15_14_030206
SCK GND VCC
TCK GND VCC
TCK/ GND/ VREF/
CCLK GND VREF
to locate jumper JP8 and
JP8
PROG
UG230_c15_15_030206
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