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Chapter 10: Analog Capture Circuit
Header J7
REFAB
(3.3V)
REFCD
(2.5V)
VINA
VINB
GND
VCC
(3.3V)
Spartan-3E FPGA
(N10)
(T4)
(E18)
(N7)
(U16)
(P7)
(P11)
Digital Outputs from Analog Inputs
The analog capture circuit converts the analog voltage on VINA or VINB and converts it to
a 14-bit digital representation, D[13:0], as expressed by
The GAIN is the current setting loaded into the programmable pre-amplifier. The various
allowable settings for GAIN and allowable voltages applied to the VINA and VINB inputs
appear in
The reference voltage for the amplifier and the ADC is 1.65V, generated via a voltage
divider shown in
VINA or VINB.
The maximum range of the ADC is ±1.25V, centered around the reference voltage, 1.65V.
Hence, 1.25V appears in the denominator to scale the analog input accordingly.
74
LTC 6912-1 AMP
A
REF = 1.65V
SPI_MOSI
DIN
0
1
2
3
A GAIN
CS/LD
AMP_CS
SPI Control Interface
SCK
SPI_SCK
AMP_SHDN
SHDN
AD_CONV
AMP_DOUT
SPI_MISO
Figure 10-2: Detailed View of Analog Capture Circuit
[
]
D 13:0
GAIN
=
Table
10-2.
Figure
10-2. Consequently, 1.65V is subtracted from the input voltage on
www.xilinx.com
B
0
1
2
3
DOUT
B GAIN
Equation
(
)
V
1.65V
–
IN
×
×
----------------------------------- -
8192
1.25V
Spartan-3E Starter Kit Board User Guide
LTC 1407A-1 ADC
A/D
Channel 0
14
A/D
Channel 1
14
0
...
13
0
...
13
SDO
CHANNEL 1 CHANNEL 0
SPI Control Interface
SCK
CONV
UG230_c10_02_022306
10-1.
Equation 10-1
UG230 (v1.0) March 9, 2006
R
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