Clock Period Constraints; Related Resources - Xilinx Spartan-3E User Manual

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Clock Period Constraints

The Xilinx ISE development software uses timing-driven logic placement and routing. Set
the clock PERIOD constraint as appropriate. An example constraint appears in
for the on-board 50 MHz clock oscillator. The CLK_50MHZ frequency is 50 MHz, which
equates to a 20 ns period. The output duty cycle from the oscillator ranges between 40% to
60%.

Related Resources

•
Spartan-3E Starter Kit Board User Guide
UG230 (v1.0) March 9, 2006
NET "CLK_50MHZ" LOC = "C9"
NET "CLK_SMA" LOC = "A10" |
NET "CLK_AUX" LOC = "B8"
Figure 3-2: UCF Location Constraints for Clock Sources
# Define clock period for 50 MHz oscillator
NET "CLK_50MHZ" PERIOD
Figure 3-3: UCF Clock PERIOD Constraint
Epson SG-8002JF Series Oscillator Data Sheet (50 MHz Oscillator)
http://www.eea.epson.com/go/Prod_Admin/Categories/EEA/QD/Crystal_Oscillators/
prog_oscillators/go/Resources/TestC2/SG8002JF
www.xilinx.com
| IOSTANDARD = LVCMOS33 ;
IOSTANDARD = LVCMOS33 ;
| IOSTANDARD = LVCMOS33 ;
= 20.0ns HIGH 40%;
Related Resources
Figure 3-3
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