Appendix C: Master Ucf Listing; Kc705 Board Ucf Listing - Xilinx KC705 User Manual

Master UCF Listing
The KC705 board master user constraints file (UCF) template provides for designs
targeting the KC705 board. Net names in the constraints listed below correlate with net
names on the latest KC705 board schematic. Users must identify the appropriate pins and
replace the net names below with net names in the user RTL. See UG625, Constraints Guide
for more information.
Users can refer to the UCF files generated by tools such as Memory Interface Generator
(MIG) for memory interfaces and Base System Builder (BSB) for more detailed I/O
standards information required for each particular interface. The FMC connectors J2 and
J22 are connected to 2.5V V
customer-specific circuitry, the FMC bank I/O standards must be uniquely defined by each
customer.
Note:
Kintex-7 KC705 Evaluation Kit product page (www.xilinx.com/kc705), Doc & Designs tab, for the
latest versions of the FPGA pins constraints files (UCF and XDC files).

KC705 Board UCF Listing

NET SFP_TX_DISABLE
NET USER_SMA_GPIO_P
NET USER_SMA_GPIO_N
NET SDIO_SDWP
NET SDIO_SDDET
NET SDIO_CMD_LS
NET SDIO_CLK_LS
NET SDIO_DAT2_LS
NET SDIO_DAT1_LS
NET SDIO_DAT0_LS
NET SDIO_CD_DAT3_LS
NET FMC_LPC_LA12_P
NET FMC_LPC_LA12_N
NET FMC_LPC_LA13_P
NET FMC_LPC_LA13_N
NET FMC_LPC_LA16_P
NET FMC_LPC_LA16_N
NET FMC_LPC_LA15_P
NET FMC_LPC_LA15_N
NET FMC_LPC_LA14_P
NET FMC_LPC_LA14_N
NET FMC_LPC_LA01_CC_P
NET FMC_LPC_LA01_CC_N
NET FMC_LPC_LA00_CC_P
NET FMC_LPC_LA00_CC_N
NET FMC_LPC_CLK0_M2C_P
NET FMC_LPC_CLK0_M2C_N
NET SI5326_INT_ALM_LS
NET HDMI_INT
NET FMC_LPC_LA10_P
NET FMC_LPC_LA10_N
NET FMC_LPC_LA11_P
NET FMC_LPC_LA11_N
NET FMC_LPC_LA09_P
NET FMC_LPC_LA09_N
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
banks. Because each user's FMC card implements
cco
The constraints file listed in this appendix might not be the latest version. Always refer to the
LOC = Y20 | IOSTANDARD=LVCMOS25; # Bank
LOC = Y23 | IOSTANDARD=LVCMOS25; # Bank
LOC = Y24 | IOSTANDARD=LVCMOS25; # Bank
LOC = Y21 | IOSTANDARD=LVCMOS25; # Bank
LOC = AA21 | IOSTANDARD=LVCMOS25; # Bank
LOC = AB22 | IOSTANDARD=LVCMOS25; # Bank
LOC = AB23 | IOSTANDARD=LVCMOS25; # Bank
LOC = AA22 | IOSTANDARD=LVCMOS25; # Bank
LOC = AA23 | IOSTANDARD=LVCMOS25; # Bank
LOC = AC20 | IOSTANDARD=LVCMOS25; # Bank
LOC = AC21 | IOSTANDARD=LVCMOS25; # Bank
LOC = AA20 | IOSTANDARD=LVCMOS25; # Bank
LOC = AB20 | IOSTANDARD=LVCMOS25; # Bank
LOC = AB24 | IOSTANDARD=LVCMOS25; # Bank
LOC = AC25 | IOSTANDARD=LVCMOS25; # Bank
LOC = AC22 | IOSTANDARD=LVCMOS25; # Bank
LOC = AD22 | IOSTANDARD=LVCMOS25; # Bank
LOC = AC24 | IOSTANDARD=LVCMOS25; # Bank
LOC = AD24 | IOSTANDARD=LVCMOS25; # Bank
LOC = AD21 | IOSTANDARD=LVCMOS25; # Bank
LOC = AE21 | IOSTANDARD=LVCMOS25; # Bank
LOC = AE23 | IOSTANDARD=LVCMOS25; # Bank
LOC = AF23 | IOSTANDARD=LVCMOS25; # Bank
LOC = AD23 | IOSTANDARD=LVCMOS25; # Bank
LOC = AE24 | IOSTANDARD=LVCMOS25; # Bank
LOC = AF22 | IOSTANDARD=LVCMOS25; # Bank
LOC = AG23 | IOSTANDARD=LVCMOS25; # Bank
LOC = AG24 | IOSTANDARD=LVCMOS25; # Bank
LOC = AH24 | IOSTANDARD=LVCMOS25; # Bank
LOC = AJ24 | IOSTANDARD=LVCMOS25; # Bank
LOC = AK25 | IOSTANDARD=LVCMOS25; # Bank
LOC = AE25 | IOSTANDARD=LVCMOS25; # Bank
LOC = AF25 | IOSTANDARD=LVCMOS25; # Bank
LOC = AK23 | IOSTANDARD=LVCMOS25; # Bank
LOC = AK24 | IOSTANDARD=LVCMOS25; # Bank
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Appendix C
12 VCCO - VADJ_FPGA - IO_0_12
12 VCCO - VADJ_FPGA - IO_L1P_T0_12
12 VCCO - VADJ_FPGA - IO_L1N_T0_12
12 VCCO - VADJ_FPGA - IO_L2P_T0_12
12 VCCO - VADJ_FPGA - IO_L2N_T0_12
12 VCCO - VADJ_FPGA - IO_L3P_T0_DQS_12
12 VCCO - VADJ_FPGA - IO_L3N_T0_DQS_12
12 VCCO - VADJ_FPGA - IO_L4P_T0_12
12 VCCO - VADJ_FPGA - IO_L4N_T0_12
12 VCCO - VADJ_FPGA - IO_L5P_T0_12
12 VCCO - VADJ_FPGA - IO_L5N_T0_12
12 VCCO - VADJ_FPGA - IO_L6P_T0_12
12 VCCO - VADJ_FPGA - IO_L6N_T0_VREF_12
12 VCCO - VADJ_FPGA - IO_L7P_T1_12
12 VCCO - VADJ_FPGA - IO_L7N_T1_12
12 VCCO - VADJ_FPGA - IO_L8P_T1_12
12 VCCO - VADJ_FPGA - IO_L8N_T1_12
12 VCCO - VADJ_FPGA - IO_L9P_T1_DQS_12
12 VCCO - VADJ_FPGA - IO_L9N_T1_DQS_12
12 VCCO - VADJ_FPGA - IO_L10P_T1_12
12 VCCO - VADJ_FPGA - IO_L10N_T1_12
12 VCCO - VADJ_FPGA - IO_L11P_T1_SRCC_12
12 VCCO - VADJ_FPGA - IO_L11N_T1_SRCC_12
12 VCCO - VADJ_FPGA - IO_L12P_T1_MRCC_12
12 VCCO - VADJ_FPGA - IO_L12N_T1_MRCC_12
12 VCCO - VADJ_FPGA - IO_L13P_T2_MRCC_12
12 VCCO - VADJ_FPGA - IO_L13N_T2_MRCC_12
12 VCCO - VADJ_FPGA - IO_L14P_T2_SRCC_12
12 VCCO - VADJ_FPGA - IO_L14N_T2_SRCC_12
12 VCCO - VADJ_FPGA - IO_L15P_T2_DQS_12
12 VCCO - VADJ_FPGA - IO_L15N_T2_DQS_12
12 VCCO - VADJ_FPGA - IO_L16P_T2_12
12 VCCO - VADJ_FPGA - IO_L16N_T2_12
12 VCCO - VADJ_FPGA - IO_L17P_T2_12
12 VCCO - VADJ_FPGA - IO_L17N_T2_12
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