HP 3562A Service Manual page 527

MO D E L 3562A
C . FPP Diagnostics Descriptions
The FPP d i agnostics perform the fol lowing functions:
1 . FPP Fu nction Test
When the FPP FU NCTN key is p ressed, the A2 System C P U loads test data i nto the
A8 G lobal RAM. The system C P U then com m ands the F P P to perform a floating point
complex m u lt i p l ication.
2 . Command Poi nter Test
The COMAND PO I N TR key i n itiates an echo test between the command poi nter
registers (U505, U 506) and the F P P status stored in global RAM. T h i s test verifies the
com mand poi nter reg iste rs, the OT ACK c i rcu it, the FPP i nterrupt and the g lobal data
output registers (U41 2, U41 4, U 51 2, U 51 4).
The system C P U sets up a com m and stack contai n i n g the echo i n stru ction in g lobal
RAM. The system CPU then writes the add ress where the command stack is stored
i nto the command poi nter registers. The FPP sends the same add ress to g l obal Ram
u s i n g the ALUs and gl obal bus i nterface c i rcu its. When the FPP is f i n is hed with the
operation, it sends an i nterrupt (I RQT3 L) to the system C P U . The system C P U tests
the FPP status in g lobal RAM and any errors in the status are d is p l ayed .
If the i nterrupt is not received by the system C P U before a cou ntdown loop is
com p l eted, the system CPU tests the FPP status in global RAM. Any errors i n the status
and an FPP i nterrupt fai l u re are d i s p l ayed .
3. J u m per E cho Test
The j u mper echo test is u sed when the com mand poi nter test does not te rm inate
(no message is d isplayed). The ju mper echo test performs the same test as the command
poi nter test except the A2 CPU does not load test data i n the A8 G l obal RAM. The
j u m per echo test is i nvoked by setting A7 J 2 B to test pos ition (w ith the power on) and
resetting the FPP. The j u m per echo test forces the FPP to perform the echo command.
If the command poi nter test fa i l s to function, the j u m per echo test may function.
4. B lock Set Test
This test uses the 'set constant command' of the FPP to test the global add ress registers
(U51 0, U51 1 ). Com pl ementary patterns are written to global RAM at address locations
which d iffer by one address bit. The system CPU verifies the resu lt. For this test, the
global data bus output registers (U41 2, U41 4, U51 2, U51 4) are assu med to be operati ng
correctly.
S E RV I C E
8-77