HP 3562A Service Manual page 228

M O D E L 3562A
This section provides the overal l instru ment description and the detai led description of
6 - 1 INTRODUCTION
each assembly to a functional b lock. The overall instru ment description describes the
interaction of the H P 3562A's individual assem bl ies. Use this section to gain an overa l l
u n derstanding of the H P 3562A's operation. Use the circuit descriptions along with the
schematics in Section IX to u nderstand the operation of an assembly. Refer to the end .. . . . . .. . .. . . . . . . . . . . . . .. . . . .
To understand the operation of the H P 3562A, the measurement it makes m u st be
6-2 OVERALL . INSTRUMENT DESCRIPTION
u nderstood . The H P 3562A uses the Fast Fourier Transform (FFT) algorithm to make
frequency domain measurements. The FFT algorithm takes time domain data and operates
on it to prod uce a frequency spectrum . Recall that the Fou rier transform, of which the
FFT is a special case, states that al l time domain waveforms can be represented as a
summation of sine waves i n the frequency domai n.
Sin ce the FFT is a special case of the more general Fourier transform, it req u i res special·
d ata col lection requirements in order to operate. A l l the numerical val ues associated with
the FFT such as sample rate, number of frequency data points, time required for a complete
convers ion, and others are all related to powers of two. For example, a time record is
defined to be N consecutive, eq ually spaced samples of the input where N is a m u ltiple
of 2. This time record is transformed as a complete block into a complete b l ock of
frequency l i nes. With a Dynamic Signal Analyzer we do not get a val id result u ntil a full
time record has been gathered.
Taking a simple look at an FFT dynamic signal analyzer, the hardware can be characterized
as a d igital waveform recorder with a great amount of com putation power. This view is
i l l ustrated by the waveform recorder diagram in figu re 6-1 .
scaling and then converted to d igital data by the ADC (Analog to Digital Converter)
assembly. The input and ADC assemblies receive the signals to control the ampl itude scaling
and conversion from the front end interface. The front end interface is programmed directly
from the CPU (Central Processing U nit). The digital output of the ADC is then stored into
RAM and displayed. H P-I B is included for remote contro l and a keyboard for local control.
In figure 6-2, the instrument is expanded to include two separate input sections and ADCs.
A sou rce is also included to m ake network measu rements. All measu rement assem b l ies
are connected to the CPU through a common bus.
SECTION VI
CIRCUIT DESCRIPTION
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C I RC U I T D E SC R I PT I O N S
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6-1