HP 3562A Service Manual page 494

S E RV I C E
A. Local Oscillator Diagnostics
When the LO FU NCTN key is pressed, the LO fu nctional self-tests cause the phase
accu m u lator and the s i n e ROMs to output a value to the A2 System C P U . The system
C P U compares the value to a known good val ue. The tests are executed twice. The fi rst
execution of the tests substitutes c lock s ignals ( I nt C l ock) generated in the LO assem bly
for the external c l oc k (Ext C l ock) signals SYNC2 and 1 0.24 M H z . The second execution
of the self-tests uses the external c locks. Perform the LO f u n ctional test by pressing the
HP 3562A keys as fo l lows:
SPC l
. . . . . . S E RV I C
feTN
Use the fol lowing descriptions to help isolate the fai l u re:
1 . LO I nterface Test
This test verifies the System Bus I nterface su bblock by read ing data to and from the
P I A (A4 U36). If 'LO I nterface Test FA I LS' is d is p l ayed, start tro u b l eshooting with
components A4 U36, U32, U33, U37, and U24 i n the System Bus I nterface Subbl ock.
LO Ti meout 'messages'
An LO timeout message can be caused by one of several compon ents fai l ing in the
system bus interface, contro l , and t i m i ng c i rc u its . However, the p robable cause of
the fai l u re is A4 U36, and U37 in the system bus i nterface or A4 U 5 5 , U56, U68, U46,
U51 , and U1 4 in the control and tim i ng c i rc u its.
2 . I nternal a n d External C l ocks
The external c l ock test uses the 1 0.24 M H z c lock from the A31 Trigger and the SYI \l C2
from the A6 Digital Fi lter (norm a l operati ng cl ocks). The i nternal clock test su bstitutes
these c locks for c l ocks gen erated on the LO assem b ly. The i nternal c locks are
s i g n ificantly s l ower than the external c l ock s i g n a l s .
I f t h e fai l u re message is 'LO E xt C lock Phase Val ues FA I LS', ' LO Ext C lock Output
Val ues FA I LS' and the other LO self-tests pass, the external c locks are fai l i ng. Start
troubleshooting with the SYNC2 and 1 0.24 M H z i nput c i rcu its (A4 U75, U68). This fail u re
can also be caused by t i m i n g problems throughout the assembly s i nce the external
signals are at a h igher frequ ency than the i nternal s ignals.
If the fai l u re message is 'LO I nt C lock Phase Val ues FA I LS', 'LO I nt C lock Output Val ues
Fai ls' and the other LO self-tests pass, the i nternal clocks are fa i l i ng. If this occurs,
the pos s i b l e fai l i ng compone nts are A4 U32 and U36 i n the system bus i nterface, A4
U68, U72, U74, and U75 i n the control and t i m i ng c i rc u its.
If the LO I nterface Test passes and both the external and i nternal c lock tests fai l , the
problem is probably not in the system bus interface or the control and t i m i n g c i rcu its.
8-44
T E ST . . . . . . T E ST
SOURCE LO
FUNCTN
MOD E L 3562A