HP 3562A Service Manual page 256

MOD E L 3 562A
6-5 A3, ROM
The A3 ROM board functions as an extension of read only memory for the system CPU
board . The ROM board stores most programs for the HP 3562A exce pt i n itial start-u p
routi nes. A l l com m u n i cations between the system C P U board and the ROM board occu r
over the system bus. Refer to the timing diagram (figure 6-A3a), block d iagram (figure 6-A3b),
and the schematic (fi g u re 9-A3) as refe renced in the fo l l owing c i rc u it descriptions.
The fol lowing descri pti ons apply to the c u rrent ROM board . This board al l ows flexi b i l ity
in the n u m ber and type of ROM c h i ps u sed . ROM density (si ze) is selected by pl acement
of j u m pers i n the O E L l i ne to the ROM c h i ps, the add ress comparator section, the delay
section, and the ROM decoder secti o n .
Address Comparator
The address comparato r verifies that the ROM board is add ressed and asse rts the ROM
se lect (ROMS E LL) l i ne low . T he ROMS E LL signal does the fol lowing;
1 . Returns DT ACK L to the system C P U to ack nowledge that the RO M board was addressed.
2 . E n ab les the ROM Decoder.
E n ables the Data Bus Driver.
3.
ROM Decoder
The ROM decoders (U21 , U22, and U 23) a re 1-of- 8 decoders. They generate the c h i p enable
(C E1 L through CE 20L) signals by deco' d i ng system add ress l i nes A1 6 through A21 . The c h i p
e n a b l e s i g n a l causes t h e selected R O M p a i r to put data o n the d ata bus.
Delay
U 1 3 and U1 4 are used to delay the DTAC K L s i g n a l based on the speed of the s l owest
com ponent on the ROM board . The p i acement of RSO determ i nes the iength of the deiay
(from 0 to 4 cl ock cyc les).
.
. ,
.. ' , 'MimQJ!y� -·
-
The memory section of the A3 ROM board co
The c h i ps are add ressed by system a d d ress l i nes A1 through A1 6 and enab led by CE1 L
th rou gh C E20L. The i nve rti ng d r ivers pass the system add ress l i nes from the system b u s
to a l l ROMs. T h e memory is arranged as a lower byte (DO through 0 7 , stored i n U1 01
through U1 20) and an u pper byte (08 through 01 5; stored in U201 through U220). Eac h
C E l i ne enab les a l ower byte c h i p a n d a n u pper byte c h i p to p u t a l l s ixteen data b its on
the bus s i m u ltaneously.
Data Bus DrIver
When enab led by the ROMS E L L s i g n a l , the data bus d r ivers transfer data from the ROM
d ata b u s to the system data bus.
.. '_. '
: :... -
- = :.�
'.--� ' � -
- -
-
. '. - - .- - .�- '- '-' 0-'
�
sists of 32k by 8 bit read-on ly-memory ch ips.
C I RC U I T D E SC R I PT I O N S
.. - =
' -
= - - - .�
- .• � = �
6-3 3