HP 3562A Service Manual page 326

MOD E L 3562A
Trigger Clock Circuit
(Refer to f i g u re 6-A31 b) The trigger c l ock c i rcuit prod u ces the 10.24 M H z c lock u s i n g a
vo ltage contro l led crystal osc i l l ator (VCXO). When the re is no external reference s ignal
(REF I N) the phase lock loop is not u sed. The error voltage i nto the PLL gain and shaping
s u bb l ock i s zero. The freq uency adj u stment is used to adj u st the frequ e n cy out of the
VCXO to precisely 20.48 M H z . This s i gnal is d ivided by two to form the 1 0.24 MHz c l oc k .
T h e 1 0.24 M H z s ignal is divided by forty to prod uce t h e internal sample signal (CONV,
256 k H z). The convert mu ltiplexer sel ects the i nternal sam ple s i gnal or an external sam­
ple s ig n a l . The si gnal S E LXS from the s h ift reg ister determi nes w h i c h is selected.
The phase lock loop is used when there is an external refere nce sign a l . The exte rnal
reference s i gnal can be 1 ,2,5, or 1 0 M H z . The difference i n freq uency between the 3.41 3
M H z harm o n i c of the external refere nce and the 3.41 3 M H z output of the VCXo are used
for the phase comparison. The sam ple r subbl ock sam p l es the 3.41 3 MHz c l ock from the .
VCXO with R E F I N
the reference s ignal's harmon ics. These frequenc ies are then put through a band pass fi lter
to prod u ce an 80 k H z s i g n a l .
A t the s a m e time the 80 kHz s i g n a l i s b e i n g produ ced, the R E F I N is d ivided by 1 2 5 . The
phase detector samples the 80 k H z s ignal with the RE F I N
ror voltage. The error voltage is ampl ified and passed through a switc hab l e low pass fi lter
to generate the control s ignal for the VCXo. When the ph ase lock loop is in lock this
control voltage is a d c val ue. I f the phase lock loop is not locked, the co ntrol voltage
deviates high and low u nti l the phase lock loop locks.
Switchable Low Pass Filter
(020 1 , R2 1 4, C207, C208J
D u ri n g normal operation the l ow pass fi lter has a very narrow bandwidth ( = 1 6 Hz). T h i s
bandwid th can change to a w i d e bandw idth ( = 4 kHz) to a l l ow f o r a faster phase loop
l ock up. When the phase loop is in lock the output of the lock detect subblock is a negative
dc voltage and a FET s w itch (Q201 ) in the P L L gain and shap i n g s u bb l o c k is tu rned off.
I f the phase loop is not in lock the o u tput of the lock detect s u b b l ock goes pos itive tu rn­
i ng the F E T switch on. This switches out the low pass f i lter and the U N LOCK s i g n a l is
sent out to ind icate the phase Iock is u n l ocked. When the output ofthe lock detect retu rns
to a steady po
s
3 to prod uce the sum and d ifference freq uenc ies of the c l ock and
+
t v
i i e
C I RC U I T D E SC R I PT I O N S
+ 1 2 5 signal to prod uce an er­
pass
low fi lter changes
6-1 09/6-1 1 0