HP 3562A Service Manual page 250

C I RC U I T D ESCR I PTIONS
4. The system processor asserts upper d ata strobe (UDSL) and/or l ower data strobe (LDSL)
signals to transfer byte data (8 bits) or word data (1 6 bits). The assembly being addressed
determi nes whether UDSL or LDSL are used.
5 . The assembly reads the system data b u s and performs the operation.
6. When the assembly has fin ished the operation, it sends the system CPU an interru pt
(I RQT).
The system processor controls the mon itor memory by asserting the add ress l ines to the
On-Board Memory Operations
m emory and the add ress decoder. The address decoder decodes these l i nes to select the
ROM or RAM memory pair to be accessed. Next, the system processor asserts the upper
data strobe (UDSL) or lower data strobe (LDSL). UDSL selects the u pper memory and LDSL
selects the lower memory. Both UDSL and LDSL are asserted at the same time if a 1 6 bit
word is used. The read/write (R/WL) signal is also decoded and determ i nes whether a read
or write operation to memory is to occu r. For the mon itor memory to communicate with
another assembly on the system data bus, the add ress decoder must activate S BU S E N L,
p lacing the system data bus i n the i n put/output mode.
The system C PU shares the global bus with all other devices to access the global RAM.
Interaction Between the A2 System CPU and the AB Global RAM
For this operation, the system C PU has 1 6 address l i nes, 16 data l i nes, and 4 control l i nes
connected to the global bus. The system CPU's global add ress b u s connection (CA1 L to
C A 1 6L) is an extension of the lower 1 6 b its of the CPU add ress bus. When the system
C P U add resses a global RAM memory location, the system CPU's address decoder asserts
the global req uest (C LRQTL) l ine to the handshake circu it. The handshake circuit sends
the memory request (MR68L) to global RAM. The global RAM retu rns a memory grant
(MC 68L) when it gives bus control to the system CPU. This memory grant signal clears
the memory request signal (MR68L) and enables the assertion of the global read/write signal
(C R/CWL). When the system CPU has a write request, the assertion of C R/CWL causes
memory data to be v'/ritten onto the global data bus. For a read request, the global bus
receivers latch the i ncoming data when the global data strobe (C DSL) signal is received.
An i nterru pt is sent when an assem bly has i nformation for the system CPU, fin ishes a
process, or requests service. For exam ple, the keyboard sends the system C PU the I RQT2 L
signal when a front panel key is pressed. When an assem bly needs to com m u n icate with
the system CPU, the assembly asserts its i nterru pt req uest line ( I RQT2 L to I RQT6L). The
priority interru pt encoder informs the system processor which assem bly has interru pted
it. For a description of the interru pt request l ines, refer to paragraph 6-8, "Signal
Descriptions".
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MOD E L 3562A