HP 3562A Service Manual page 281

C I RC U I T D E SC R I PT I O NS
Sequencer (U 1 03J
The sequencer is an 'add ress sequencer' u sed to control the execution of m ic roinstru ctions
stored in the m i c rocode memory. The sequencer has the c apab i l ity of sequential access
and conditional b ranching to any m icroinstru ction i n the m icrocode memory. During each
m i c ro i nstruction, the seq uencer provi des a 1 2-bit add ress to the m icrocode memory from
one of fou r sou rces:
1 . The i n cremented present add ress.
2 . A jump add ress from the m i crocode memory o r i n struction mapping PROM.
3 . A j u m p add ress f rom a previous m i c ro i nstru ction that stored a n add ress i n a n i nternal
regi ster of the ALUs.
4. A su brouti n e retu rn add ress from the seq u e n cer's i nternal stack register.
T he seq uencer's next add ress is determ i ned by the test and j u m p PROM, the conditional
code mu ltiplexor, and the i nstru ction m apping PROM.
Global Bus Interface
T h e FPP h as the ab i l ity to read and write 1 6 and 32 b i t words to and f rom the global RAM.
W hen doing a 32 bit operation, the FPP uses two consecu tive 1 6 b it word operations. T h i s
i s accom p l ished by ad d ressing the f i rst 1 6 b i t word fo l l owed by i nverti ng GA1 L f o r the
address of the second 16 bit word. For 32 b it floati ng point d ata, the f i rst d ata word contains
t h e most sign ificant bits of a m antissa and the second data word contains the least s ign ifi­
cant bits of the mantissa and the exponent. This resu lts i n a 24 bit mantissa, 8 bit exponent,
f loating point data word .
T o start the g lobal b u s transfer, the A L U s write the global RAM add ress for the data word
o n the B bus. The bus contro l PROM uses control l i nes PLSA, PLSB, and PLSC to command
co ntrol PAL 1 and control PAL 2 to set u p the FPP ass e m b ly for a data transfer. I f the
F P P is to read a 32 b it data vv'ord from global RAt- v i, the fo l low i n g operations occ u r:
a.
b. Bit 0 of the B bus is c locked th rough the test even f l i p-flop (U21 5) to determ i ne
if the add ress is an even or odd n u m ber.
c. Contro l l i ne PLSA is c l ocked t h rough the read/wr ite f l i p-flop (U21 5) to control
PAL 2 to set up for a data read operation.
2. Control PAL 1 asserts the Memory Request FPP s i g n a l (MR F P P L) to the global RAM .
3 .
The global RAM responds by send i ng the Memory G rant F P P signal (MG FP PL) to the
FPP. T h i s causes the fol lowing to occu r:
a. The global add ress registers are enabled .
b. Contro l PA L 2 asserts the G lobal Read/Write s ignal (G R/G WL) f o r a read ope ratio n .
c . Contro l PA L 2 tests its Q1 input t o deter m i ne if this is the fi rst h a l f or second half of
the 32 bit word.
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MO D E L 3562A