HP 3562A Service Manual page 289

MO D E L 3562A
D I SP LAY DMA WO RD/AD D R E S S C O U N T E RS (A8)
The system C P U puts the beg i n n ing add ress and the length of each buffer on the system
d ata b u s . T h ey are cl ocked i nto the d isplay DMA word (U400, U401 , U500) and ad d ress
(U600, U601 , U 602, U603) counte rs by the ALOADL and WLOADL signals from the disp lay
control ler. E ach time a display memory grant is asserted, the add ress from the add ress
cou nters f l ows through the d is p l ay add ress drivers (U604, U605) to the memory add ress
m u ltiplexer. After the d isplay data has been transferred to the display i nterface board
(A1 7), the cou nt enable l i ne (COUNT E N L) is asserted low. The address cou nters i n c rement
and the word cou nters decrement by one. This p rocess conti nues u nt i l the entire buffer
has been transm itted to the d is p l ay interface. The word cou nters have go ne to zero,
asserti ng the TC L (ter m i nate cou nt) l i ne low. T h i s signal generates an i nterrupt to i nform
the system CPU that the buffer transm ission is comp lete .
D I S P LAY R E F R E S H T I M E R (A8)
The d i s p l ay m u st be refreshed at a rate of 60 H z or greater. U1 01 d ivides down the 8 M H z
clock to 61 H z . U201 is clocked by th i s 61 H z s ignal and puts out a SYNC p u l se every
1 6.4 msec. E ac h time the system C P U starts a new d isplay frame it sets D1 5 on the system
bus. T h i s s i g n a l is u sed to reset the d isplay refresh timer to coord i n ate the sync pu lses
w ith the new frame information.
D I S P LAY I N T E RFAC E (A1 7)
One section of the d isplay i nterface board buffers i nformation and control signals fro m
the global b u s to the 1 345A d isp lay. T h i s c i rcu itry consists o f two i nverting registers
(U1 , U2) for the data I i nes and a n o n-i nverti ng bus d r iver (U3) for the control l i nes.
The other section of the i nterface b oard is the output protection c i rcu itry between the
d i splay X, Y, and Z outputs and the i r res pective rear panel con nectors.
Internal Signal Descriptions
A tOA D t
. .. �'.':.=
m < " ' �. ,,�V_"._, U �
B RST l
B U S E N 1
B U S E N 2
CO
through
C7
Add ress load, active low. Al l ows t h e contents o f t h e system add ress
bus to be loaded i nto the d isplay add ress cou nter.
--��
SYNC signal.
Board reset, active low. Software reset for the global RAM board ,
originates from the system C P U .
T i m i ng signals w h i c h enable the global b u s to perform a transactio n .
Cou nter add ress b u s l i nes 0 through 7 .
C I RC U I T D E SC R I PT I O N S
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e
6-69