HP 3562A Service Manual page 282

Dynamic signal analyzer
Hide thumbs Also See for 3562A:
Table of Contents

Advertisement

MO D E L 3562A
4 .
The global RAM assemb ly places the data o n the global data b u s and activates the
G l obal Data Strobe signal (G D S L) which latches the data i nto the g l ob a l bus reg isters.
5 . The global RAM assembly sets the M G F P P L l i ne l ow to i nform co ntrol PA L 1 th at th e
fi rst half of the 32 b it data word has been loaded i nto the FPP assem b ly.
Control PA L 1 sets global add ress l i ne 1 (GA1 L) high which i n c rem ents the address
6.
to g lobal RAM by one fo r the second half of the data word.
7.
The second half of the data word is now loaded i nto the gl obal bus reg isters.
Arithmetic Logic Units (ALUsJ
The Arithmetic Logic U n its (AL U s) su bblock consists of six 4-bit sl iced arithmetic-oriented
m icroprocessors (AM2903) cascaded for up to 24-b it m athem atic operations. The A L U s
c a n do com plete arithmetic a n d l o g i c i n structions i n c l ud i ng m u l t i p l ication, d ivision, a n d
normal ization. Arithmetic a n d logic i nstru ctions are read from the A L U s i nstru ction b u s
b y the A L U s i nternal i n struction decoder.
The ALUs have a 1 6 x 24 bit RAM for storing d ata. To load the A L U s RAM, the data i n
the gl obal b u s registers i s p l aced o n the Y bus when MAN L i s active and on the B b u s
w h e n E X P L is active. The A Port Add ress f rom the m ic rocode memory dete r m i nes the
storage location of the data block add ress (u pper Y bus) and the B Port Address deter­
m ines the location of the B bus data and the location of the data com ing i n and go i n g
o u t on the Y bus.
The A L U s perfo rm operations using two operands. Mu lti plexors i n the ALUs provide
selection of various pairs for the operands which can be data from the ALUs RAM or data
from the external buses.
After the ALUs have completed an operation, several status b its are sent to the cond ition
code mu ltiplexor for testing. The status bits are as fol l ows:
7 1: D (\
L- L .,,'-'
I nd icates the ALUs Y bus output is zero (al l 24 b its)
OVR
F rom the m ost s ign ificant ALU (U31 0) ind i cati ng an operation has res u lted in an
overflow.
CN + 4
From the most sign ificant A L U (U31 0) ind icating a carry-o u t of the A L U .
C I RCU IT D E SC R I PT I O N S
6-61

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents