HP 3562A Service Manual page 273

C I RC U I T D E SCRI PT I O N S
M EA S U R E M E N T STAT E MAC H IN E
T h i s bl ock consists of five parts:
Command Reg ister
Meas u rement Co ntro l Mac h i n e
Status Register
Start/Stop Control
Trigger Contro l
T h is block, configu red by the system C P U , contro l s how the d igital fi lter assem bly works
in the various modes.
The co mmand register (f l i p-fl o ps A6 U307 and A6U1 09) is used to read data l ines from
the local data bus i nto the me asurem ent state machine. The comm and i s c l ocked i nto
t h e register by the signal WRI BCCM D L (write I BC com mand) f rom the add ress decod er.
(The d igital f i lter asse m b ly is sometimes cal led the i n p ut buffer control.) The com m a n d s
configure t h e measu rement state m a c h i ne, control t h e LO sel ection on the d igital f i l ter
bo ard, and provide i nformation to the trigger LED control b lock.
T h e measu rement contro l m. a chine senses configu ration and status signals and co ntro l s
t h e measu reme nt. When i t is configu red f o r the type of measu rement and rece ives a start
s ig nal, the measu rement control mach i n e enables the meas u rement to start. A measu re­
m e nt is com plete when O U T4 is activated . OU T4 is rec l ocked, cal led B L K FU L L H , and
con nected to an input of th e measurem ent control machi ne. The measurement is term inated
by activati ng the S E T B L K READYL signal, causing a CPU i nterru pt. The CPU decides w h e n
the transfer to RAM may b e exec uted a n d grants t he g l ob a l bus appropriate ly.
The status registe r is an eight-l ine latch w h i c h a l l ows the A1 CPU to read the status of
t h e digital fi lter assem bly. The status word is l atched onto the local data bus when the
R D I BCSTAT L signal is activated . B it 0 is a signal cal led NOTREALT I M E F LG . T h i s signal
activates when data can not be moved through the D FA fast enough to prevent d e l ay
of f u rther measureme nts. I n this case, the data i n glo bal RAM is not updated fast e n o u g h
to be real time. T h i s flag is reset every ti me the status \vo rd is read . I f t h e cond ition i s
stii l not real time, the reset does not c h a nge the status o f t h e NOT R E A LT I ME FLG s i g n a l
(C LR overrides a S E T com m and).
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m easu reme nts. I n a triggered meas u rem ent the d igital fi l ter beg i ns processing d ata and
storing it i n RAM when the trigger board senses the trigger signal. There is also some inter­
action with the sou rce. Here is an example sequence of events for a triggered measurement:
I f pretrigger delay is active, d ata is taken before a trigger s ignal is rece ived . I f
pretrigger delay is 1 00 samples, the cou nter keeps track of t h e nu mber of s a m p l e s
and the trigger s i g n a l is ignored u nt i l at le ast this m any samp les are taken. O U T1
is active when pretrigger delay is com plete. The trigger control IC recogn izes t h i s
a n d a r m s the trigger by activating the ARML s ig n a l . T h i s signal goes to t h e d igital
sou rce which is waiti ng for a trigger.
When the d i gital source rece ives the trigger it activates the s i g n a l B FST (buffer
start) going back to the trigger control l e r on A6.
6-52
MOD E L 3562A
are used to control triggered