HP 3562A Service Manual page 349

C I RC U I T D E S C R I PT I ONS
DATA1
DATA2
DAV
DAVL
D I SPLAY OUTPUT X, Y, Z
DMADTACKL
D R E L
DSA SS
6-1 34
DATA1 , DATA2
(A32, A34 TP61 0)
These two s ignals are the serial d ata streams from the A32, A34 Analog
Di gital Converters to the AS D igital F i l ter. Data transfer begins th ree
clock cycles after the assertion of D R E Q L and o c c u rs at a 1 0 .1 4 M H z
rate. T h e f i rst b it i s t h e data val id b it, fo l lowed b y the overload status
bits, the n the 1 3 bit serial data with the L S B fi rst.
DATA VAL I D
Signal to and from the A 2 System C P U to the A22 H P-I B . T h i s l i ne is
used i n the H P-I B handshake seq u ence.
DATA AVA I LA B L E
Active Low
The AB G l obal RAM sends the A1 7 Display I nterface this control s ignal
after it writes the d ata for the HP 1 34SA i nto the A 17 Display I nterface
registers. The A 1 7 Display I nterface then sends DAVL to the H P 1 34SA
which te l l s the d i s p l ay that data is ava i l ab l e . DAV L works with R F D L
(Ready F o r Data) t o transfe r data to t h e H P 1 34SA d is p l ay. Refer to
the H P 1 34SA serv i ce m a n u a l section 3-6 for the handshake t i m i n g
i nformation.
T hese s i gnals are outputs of the H P 1 34SA d is p l ay. Refer to the
H P 1 345A operating and service manual for troubleshooting and adjust­
ing the d i s p l ay.
DMA DATA T RA N S F E R AC K N OW L E DG E
Active Low
This signal is from the AS Digital Fi lter to the A6 D igital F ilter Contro l ler.
When a 'read fi lter status' command or a read/write to a AS DMA
control ler register is comp leted, DMADT ACK L goes low. The A6 Digital
Fi lter Contro l l e r then sends DTAC K L to the A2 System C PU to i n d icate
the comm and is c o m p l eted .
c Ive ow
When the AS D igital Fi lter is ready for data, it sends the D R E Q L signal
to the A32, A34 A na l og D i g i ta l Converters. The d igital f i l ter expects
the data back on the forth c l ock cyc le after the D R E Q L. T h i s s i g n a l
is also sent to the A 1 Digital Source. T h e d igital source u ses the D R E Q L
to syn c h ronize t h e buffer start signal (B FST) go i n g to the A6 D ig ital
Fi lter Contro l ler with the s a m p l e signal (SAM P) from the A34 A n a l og
D igital Co nverter.
DSA START/STO P
(AS T P1 3, A6 T P7)
This signal corresponds to bit 2 of the AS Dig ital F i lter ass e m b ly
comm and register. The AS D igital F i l ter and the A6 D igital F i l ter
Control ler u se the DSA SS signal for d i agnostic testi n g .
MOD E L 3S62A
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