HP 3562A Service Manual page 334

C I RC U I T D E SCR I PT IO N S
Offset C/A Converter
U201 is a D/A converter connected to the data path at the output of amp 4 (U1 01 ) to
correct the accu m u l ated dc offset of the ampl ifiers. This process occurs du ring auto zeroing.
The offset control information comes onto the board as serial data through U603, U203
and U202. U202 converts the offset DAC information to para l l e l format and latches it.
Over Range/Half Range Circuit
T h i s circu it com pares the signal at the output of U S01 (wh i c h is the s ignal .from the data
path at TP1 00, ampl ified X4) to a fixed voltage reference to generate the overload (OVLD)
and half range (H LFSCA L E ) signals. T h i s is done with com parators U SOO and US02. (N ote
that the s ignal from US01 also leaves the board as the trigger s ignal TR I G @). The
c o m parators of USOO are configu red to trigger on the positive portions of the signal as
U502 triggers on the negative. The ou tputs of both are w i re OR'd together . The COVLD
s ig nal from the i n p u t board is OR'd with the overl oad signal from the ADC board so that
either cou ld activate the OVLD s i g n a l .
Missed Sample Circuit
I f an external sam p l e signal is used w h i c h is too fast, the MSMP s ignal is sent to the d i gital
f i l ter control l e r. The m i ssed sam p l e c i rc u i t d igita l ly dete r m i nes if the track and hold is
h o l d i ng a signal at the time a CONY s ignal is rece ived .
D iagnostic Tester
T h e ADC contro l l er (U602) is a c ustom b u i lt state machine. Prob l e m s with this part m ay
be di agnosed by using self tests w h i c h are activated by front panel key p resses. Configu ra­
t i o n commands and test signals are sent to the ADC board as serial d ata through the
s e r i a l/paral l e l s h ift register U603, so the self tests a l so c heck the CNTLDAD (contro l d ata)
path.
Master/Slave Selection
T h e re is an ADC board in each analyzer input c h a n n e l . These are identical board s. The
digitizing process m ust occur simu ltaneously on both boards, so one contro l l e r m ust control
the end of conversion (EOC) and the p r o cess switc h (G SW) s i g n a l s to the other contro ll er
so it can synchronize its operations with the contro l l i ng board . I f no ADC board is instal led
in c hannel two, the control ler on the board in channel 1 controls its own A/D convers ion.
The s l ots on the m other board for the ADC boards are w i red so that the contro l l e r on
the board i n channel two contro l s the AID co nvers ion p rocess on both boards. The
master/sl ave c i rc u it on each board c o n sists of an inverter (U S03d) with a p u l l up res iste r
o n the input. The mother board connects the output of this c i rc u it of the board i n the
c hannel two s l ot to the i n pu t of the same c i rc u it on the board in the channel one s l ot
(they both control buffers U604 and USOS on the i r respective boards, too). When boards
are instal led i n both s l ots, the board in s l ot two has a l ow l e v e l on the m aster/s l ave l i ne
w h i c h feeds the input of the inverter on the board in s l ot one, resu lting in its master/sl ave
I i n e being high. When the channel two ADC board slot is em pty the ADC board in channel
one automati cal ly becomes the " m aster"; it takes control of its own conversion process.
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MO D E L 3S62A
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