HP 3562A Service Manual page 288

C I RC U I T D E SC R I PT I O N S
Dynamic Memory Array
T h e RAM itse lf is a 64k by 1 6 b it dynam i c memory array constru cted from 1 6 64k by
1 b it dyna m i c RAM chips . The 1 6-p i n RAM c h i ps have 8 add ress i n put l ines and req u i re
add ress mu ltip lexing to receive 1 6 add ress bits.
Address Multiplexer and Address Drivers
T h e add ress mu ltiplexer (U61 1 and U 61 2) mu l t i p l exes the 1 6 gfobal add ress l i nes and
transfers the add ress 8 bits at a time to memory through the memory add ress drivers (U1 1 1
a n d U21 1 ).
Memory Control Drivers
T h e memory co ntrol c i rcuit generates the row add ress strobe (RAS L L and RAS U L) and
c o l u m n address strobe (CAS L L and CAS U L) signals. These are c l ock s i g n a l s which strobe
the m u ltiplexed add ress i nto the RAM .
Memory Refresh Timer and Refresh Address Counter
T h e dyn a m i c gl obal m emory m u st be refreshed to pre � ent loss of data. E very 8.5
mem ory refresh timer (U404) sends a memory refresh req u est (M RRFSH L) to the arbiter.
W hen the arb iter issues a memory refresh grant (MG RFSH L), the output of the add ress
mu lti plexer is d isabled. The refresh add ress cou nter (U51 1 and U51 2) is enabl ed . The output
is a p p l ied to the m e m o ry add ress d rivers to set up the m e mory row to be refreshed. The
row add ress strobe s i gnals (RAS U L and RAS L L) are enabled and a read mem ory ope ration
refreshes the RAM me mory row .
Global Bus Transceivers
T h e global bus transceivers (U609 and U61 0) are b i-d i rectional, i nverti ng buffers w h i c h
transfer data betwee n the global d ata b u s and memory l ocations. T h e RAMG R/G WL signal
determ i nes the d i rection of flow (if h igh, the transaction is a read cyc le; if low, it i s a
write cyc ie).
The d i s p l ay is p rese nted to the viewe r in the form of a frame. A frame consists of from
3 to 20 buffers (e.g. data, grid, sca les). E ach of these buffers has a p redef i ned s ize and
l ocation in global memory. The d is p l ay co ntro l/i nterface section mon itors and d i rects the
f l ow of this data to the 1 345A display i n response to control commands from the A2 System
C P U .
D I S PLAY CONTRO L L E R (A8)
The d is p l ay contro l l e r (U 303) is a f i e l d p rogrammable logic seq uencer or state m a c h i n e .
A m o ng the i n puts to the disp l ay contro l l e r are address a n d control l i nes from the system
b u s . The syn c h ro n i z i n g register (U302) syn c h ro n izes the control i n puts with the 8 M H z
c l ock from the system C P U .
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MOD E L 3562A
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