HP 3562A Service Manual page 352

MO D E L 3562A
G R/GWL
G RAM RST L
G SMPLL
G SW
H D1 to H D8
H IG H I N P UT 1
H IG H I N P UT 2
The g l obal b u s consists of the fol lowing s ignals:
G DOL to G D1 5 L . . . . . . g lobal data bus
GA1 L to GA1 6 L . . . . . . g l obal add ress b u s
G DS L . . . . . . . . . . . . . . . g lobal data strobe
G R/G WL . . . . . . . . . . . . g lobal read/gl obal write
Memory Req u est l i nes M R F FTL, MRDF2 L, MRDF1 L, MR68L , and
M R F P P L.
Memory G rant l i nes MG FFT, MG DF2 L, M G D F1 L, MG68 L, and
MG FPPL.
G LO BAL READ/G LO BA L W R I T E
Active Low
When low, this open col lector signal def i nes the g l obal d ata bus
transfer as a w rite cyc le. When it is high, the transfer is a read cyc le.
G LO BAL RAM R E S E T
Active Low
S ignal from the A2 System C P U to the A8 G lobal RAM. When power
is app l ied to the i nstrument or A2 S1 is activated, G RAMRSTL goes
low and resets the global RAM. T h i s signal is used to reset the g l obal
RAM instead of R E S ETL, so a software reset does not reset the
A8 G lobal RAM
G LOBAL SAM P L E
Active Low
At this time, this s ignal from the A8 G lobal RAM is n ot used by any
assem bly in the i nstrument.
PASS GA I N SW I TC H
(A32, A34 TP604)
This s ignal is u sed by the A32 ADC 1 and the A34 ADC 2. GSVv' is f rom
the ADC contro l l er to the ADC process switch. I t is used with C LADC
.
to dete ' u t to th A D C
DATA
These l ines are the data l i nes between the A2 System C P U and the
A22 H P-I nterface Bus.
H I G H I N PU T 1
H I G H I N PU T 2
(A33, A35 J 300-1 )
These are the i n p ut s ignals from the f ront panel B N C centers to the
A33 . l n put 1 and A35 I n put 2 asse m b l ies.
C I RC U I T D E SC R I PT I O N S
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