HP 3562A Service Manual page 296

MODE L 3562A
C O U N T E RS O N E A N D TWO
Add ress generation beg ins with two cou nters. Counter One (U209
Cou nter Two (U409-U41 1 ) is a l oadab l e, cou nt-up or count-down cou nter on the i nternal
d ata bus. Cou nter Two appears as a w rite-only port to the TMS320 system . Typ ical ly, one
cou nter is used to keep track of i n p ut add resses while the other is u sed to
of output addresses. The output of one of the two cou nters is selected by the cou nter
m u ltip lexer (U309-U31 1 ) to d r ive the add ress count bus.
A D D R E SS TRANS LATOR
The add ress transl ator (U31 3
the address count bus to add resses on the FFT add ress bus depen d i n g o n the F FT l eve l
and whether a read or a write operation is req u i red. Several bits from the hardware control
regi ste r are used to determ ine how the data on the address cou nt bus is changed to FFT
address bus data. PAS S B I TO is a control l i n e (see sc hematic) used to m ask off the least
s i g n i f i cant bit of the add ress d u r i n g a com plex transform requ i r i ng access to o n ly even
(real) wi ndow coeff i c ient ad d resses .
PAG E REG I ST E R
T h e u pper bits of the FFT add ress b u s come from the Page Register (U31 2). T h is reg i ste r
o n the i nternal d ata bus i s a read-on ly register activated by the port decoder. I t sel ects
the RAM location for input and output blocks. The TMS320 sets the i nputs which are written
to (once) at the beg i n n i n g of the transform . The page register specif ies the four most s i g n ifi­
cant b its of the FFT add ress bus depend ent on whether the memory access i s a read or
a w rite (state of the FFTWR s ignal) and whether the i nformation being accessed is wi ndow
data or FFT data (state of the W I ND PG L signal). (User defined windows are stored i n RAM .)
CO E FF I C I E N T ROM
The coefficient ROM (U31 5 and U31 7) appears on the i nte rnal data bus as a read-o n l y
register activated b y t h e port decoder. T h e FFT add ress b u s d rives t h e ROM i np u ts. T h e
pU ipose o f t h i s c i r c u it is to co nvert FFT add ress i nformation i nto coeff i c ients u s e d by
the TMS320 system for the transform process.
There are two bu sses connected to the FFT board; the system bus and the global b u s .
E ach is composed o f add ress l i nes and data l i nes. T h e system bus a l l ows com m u n i c atio n
,between the system CPU and the TMS320 system. The global bus allows the TMS320 system
ac cess to the global RAM w h i c h h o l d s u ser def i ned wi ndow i nformation and d ata for the
Fourier transformation. The FFT board hand les a l l mem ory access d i rectly by req uesting
mem ory and contro l l i n g the global bus. The i nterface hardware consists of the fo l lowi n g
b locks:
System bus i nterface:
•
System add ress bus buffer
•
System data bus i nterface
•
FFT i nte rrupt c i rcu it
•
CPU i nterru pt c i rc u it
&
U31 4) consists of 2 PA L I Cs u sed to conve rt addresses on
G lobal bus i nte rface:
•
•
•
C I RC U I T D E S C R I PT I O N S
&
U21 0) is an up-cou nter.
'
keep track
G lobal address bus i nterface
G lobal data bus i n terface
G lobal bus handshak i n g c i rc u it
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