HP 3562A Service Manual page 294

MODE L 3562A
6-1 0 A9, FAST fOURIER TRANSfORM (ffTJ PROCESSOR
The Fast Fourier T ransform (FFT) p rocessor board performs windowi ng, Fast Fou ri e r
T ransform, a n d i nverse Fast Fourier T ransforms a s specified b y the System CPU (A2). I nput
and output data are stored in mem ory b locks i n the glo bal RAM.
the memory access (control s the global bus) to move these bl ocks to and f rom global
memory (on the global bus). I n put data may be real or com plex, for one channel or two .
The description of how the FFT works covers operation at the system level (between the
FFT board and the system C P U ) and at the board leve l . Refer to the block d iagrams i n
figu res 6-A9a a n d 6-A9b a n d the schem atic i n figu re 8-A9 f o r the fo l lowin g d i scussion of
the theory of operation.
FFT Interaction with the CPU
The FFT board is contro l led by the system CPU (A2) through the system bus. The FFT board
appears to the m a i n C P U board as a set of reg isters. These registers (sometimes cal led
pseudo-registers) exist as RAM i nside the FFT m icroprocessor c h i p .
FFT I/O i s not syn c h ronized with othe r activity o n the global b u s . T h e FFT requ ests control
of the g lobal bus for d i rect memory access (DMA) whenever it is necessary to get input
d ata or store output data. The FFT has the h ighest pri ority i nterrupt statu s i n the DMA
c h a i n . Memory access is provided with i n 500 ns of the F FT memory req uest.
FFT Microprocessor System
The FFT m i c roprocessor (U1 03) is a TMS320 ru n n ing at 5 M H z . The c rystal osc i l l ates at
20 M H z but the TMS320 d ivides that by four. The TMS320 and its ROM (U301 and U303)
form a complete m i c roprocessor syste m . The data bus between the TMS320 and its ROM
is connected to the FFT i nte mal data b u s through a transce iver. The rest of the c i rcu itry
on the board appears to this system as i n d ividual I/O ports . The ports are activated by
add ress ing combi nations w h i c h activate the port decoder. The circu its that are not d i rectly
contro l l ed by the TMS320 through the port decoder are i nd i rectly control led through the
hardware control registe r.
Port Decoder
bus. The TMS320 enab les ports through address and control l i nes w h i c h are i n pu t l i nes
for the port decoder. When an add ress correspon d i n g to a port appears on the add ress
bus and the control l i nes are enab l ed, the port decoder sel ects one of t h i rteen l i nes to
activate . These l i nes are descri bed i n the f i rst part of the i nte rnal signal descr iptions at
the end of the FFT ' c i rc u it desc ripti on.
Hardware Control Register
The hardware control register (U405 and U406) is used to control circu its that are not d i rectly
connected to the i ntern a l data bus. It appears to the TMS320 as a write-o n ly regi ster on
the i nternal data bus and is activated through the port decoder. I t a l l ows the TMS320
to control the gl obal bus I/O seq uence r, co ntro l the type of transform done, keep track
of the level and scale factor d u ring the transform, and mon itor scale factors and execution
status.
C I RCU IT D E SCR I PT I O N S
T
he FFT board performs
6-75