HP 3562A Service Manual page 299

C I RC U I T D E SC R I PT I O N S
Test Bit Mux
T h e test bit m u ltip lexer (U206) selects the the TMS320 test bit ( B I 0 320). T h i s a l l ows the
TMS320 to exam ine the scale-com pare f l i p-fl ops i n U208 and exam i ne th e PASS DON E
b i t wh i c h comes from the sequencer te l l ing the processor when execution has f i n is hed
a l eve l . It can also exa m i ne the PRN bit from U1 05 .
Pseudorandom Number Generator
T h i s c i rc u it p rovides a b it that is rando m ly high or low. The FFT processor uses this i nfor­
m ation to do a math routine cal led d ithered rou n d i ng.
LED Register
L E D reg i ster (U 202) is a write-o n ly reg i ster on the FFT i nternal data bus. It d rives the L E D
arrays CR1 01 and CR1 02. One l i ne is used as the start/stop signal for d igital signatu re analysis
(DSA). Another l i ne is u sed to c lear the pseudorandom generato r.
Internal Signal Descriptions
PORT D E CO D E R OU TPUTS
Set i nterru pt req uest to system , active low.
S I R QSYS L
Reset i nterru pt req uest to system, active low.
R I RQSYS L
G l obal data bus i n, active low.
G D B I N L
G l obal data bus out, active low.
G D B O U T l
System data bus i n , active low .
S D B U S I N L
S D B U S O U T L System data b u s out, active low.
SA B U S I N l
lD PG S L
lDHWCRL
LDCT R 2 L
C L RSCA LE L
B F S U BADL
6-80
System address bus i n , active low.
Load page register, active low.
Load hardware co ntro l register, active low.
Load cou nter two, active low.
Clears the scale data i n the pseudo-scale ROM output f l i p-fl ops, active low.
B u tterfly su broutine add ress, active low.
MO D E L 3562A