Central Synchronization Sub-System; Figure 13: 7X50 Timing Sub-System Architecture - Alcatel-Lucent 7710 SR Configuration Manual

Synchronization and Redundancy

Central Synchronization Sub-System

The timing subsystem for the SR/ESS platforms has a central clock located on the CPM
(motherboard). The timing subsystem performs many of the duties of the network element clock as
defined by Telcordia (GR-1244).
The system can select from three timing inputs to train the local oscillator. The priority order of
these references must be specified. This is a simple ordered list of inputs: {bits, ref1, ref2}. The
CPM clock output shall have the ability to drive the clocking for all line cards in the system,
however, implementation details are strongly effected by existing design. Regardless where clock
recovery is performed the recovered clock will be able to derive its timing from any three of the
following receive line ports:
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BITS/SSU BITS/SSU BITS/SSU
Pri Pri Pri
POS POS POS
0 0 0
Timing from: Ext BITS-Pri, POS Timing from: Ext BITS-Pri, POS Timing from: Ext BITS-Pri, POS
POS POS POS Line-Ter & internal oscillator Line-Ter & internal oscillator Line-Ter & internal oscillator
0 0 0
traffic traffic traffic
timing timing timing

Figure 13: 7x50 Timing Sub-System Architecture

OC3/STM1, OC12/STM4, OC48/STM16, OC192/STM64
T1/E1 or CES channel (traffic signal based — adaptive clocking)
Ethernet
BITS port on a Channelized OC3/STM1 CES CMA
1588 slave process of an Ethernet MDA
Includes the CPM/SFM complex
7710 SR OS Basic System Configuration Guide
POS POS POS
synthesizer synthesizer synthesizer synthesizer
Clk recovery Clk recovery Clk recovery Clk recovery
Sec Sec Sec
POS POS POS
2 2 2
Ter Ter Ter
1 1 1
1 1 1
Line-Sec, Line-Sec, Line-Sec,