Sun Microsystems Blade 1500 Service, Diagnostics, And Troubleshooting Manual page 161

post max max Output Comparison (Continued)
TABLE 7-7
Output Displayed
0>8k DMMU TLB 0 Data
0>8k DMMU TLB 1 Data
0>8k DMMU TLB 0 Tags
0>8k DMMU TLB 1 Tags
0>8k IMMU TLB Data
0>8k IMMU TLB Tags
0>FPU Registers and Data Path
0>FPU Move Registers
0>FSR Read/Write
0>FPU Block Register Test
0>FPU Branch Instructions
0>FPU Functional Test
0>Scrub Memory
0>Flush Caches
0>Functional CPU Tests.....
0>XBus SRAM
0>IO-Bridge SouthBridge Remap Devs
0>IO-Bridge Tests.....
0>JBUS quick check
0> to IO-bridge_1
0>IO-Bridge unit 1 sram
0>IO-Bridge unit 1 reg
0>IO-Bridge unit 1 mem
0>IO-Bridge unit 1 PCI id
0>IO-Bridge unit 1 interrupt test
0>Print Mem Config
0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
0>Memory interleave set to 0
0> Bank 0 1024MB : 00000000.00000000 -> 00000000.40000000.
0>Block Memory
test
test
test
test
What Is Happening
Translation look-aside buffers
(TLB) are tested for data and
instruction buffers.
Floating point unit (FPU) is
checked.
FPU status register is checked.
Additional FPU testing is
performed.
Memory is set to zero.
Caches are set to zero.
CPU is checked.
XBus buffer memory is checked.
I/O bridge and I/O subsystem
probe for devices.
I/O bridge is checked.
JBus communication with I/O
bridge is checked.
32K scratch pad SRAM is checked.
I/O bridge registers are checked.
I/O bridge memory is checked.
I/O bridge PCI buses are checked.
I/O bridge interrupts are checked.
Memory configuration is to be
displayed.
Cache status is displayed.
4 megabyte portion of memory is
scrubbed and tested.
Memory is checked again.
Chapter 7 Power-On Self-Test 7-17