Sun Microsystems Blade 1500 Service, Diagnostics, And Troubleshooting Manual page 154

post min max Output Comparison (Continued)
TABLE 7-5
Output Displayed
0>Interrupt Crosscall.....
0>Setup Int Handlers
0>MB: Part-Dash-Rev#:
0>Set CPU/System Speed
0>CPU Config Jumper = 00000004
0>Init Memory.....
0>Probe Dimms
0>Init Mem Controller Regs
0>Set JBUS config reg
0>IO-Bridge unit 1 init test
0>Do PLL reset
0>Setting timing to 10:1 12:1, system frequency 160 MHz, CPU
frequency 1500 MHz
0>Soft Power-on RST thru SW
0>PLL Reset.....
0>Init SB
0>Initialize I2C Controller
0>Init CPU
0>Init mmu regs
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0> Size = 00000000.00100000...
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Scrub Mailbox
0>Timing is 10:1 12:1, sys 160 MHz, CPU 1500 MHz, mem 133 MHz.
0> UltraSPARC[TM] IIIi, Version 3.4
0>Init Memory.....
0>Probe Dimms
0>Init Mem Controller Sequence
0>IO-Bridge unit 1 init test
0>Test Memory.....
0>Select Bank Config
0>Probe and Setup Memory
0>INFO: 1024MB Bank 0, Dimm Type X4
0>INFO: No memory detected in Bank 1
0>INFO: No memory detected in Bank 2
0>INFO: No memory detected in Bank 3
7-10 Sun Blade 1500 Service, Diagnostics, and Troubleshooting Manual • December 2004
3753187-01-Serial#:
What Is Happening
Interrupt handlers are set up.
Motherboard part number and
serial number is read from FRU
ID.
Jumpers for CPU and JBus
frequency are read.
Memory is initialized
Presence of DIMMs is checked.
Memory controller registers are
initialized.
JBus frequency register is set.
I/O bridge chip is initialized.
Phase locked loop (PLL) is reset.
Reconfigured frequencies are
displayed.
Soft reset.
Initializations and setups are
repeated.
New timing ratios and frequencies
are displayed.
Repeated initialization continues.
Memory is probed.