Sun Microsystems Blade 1500 Service, Diagnostics, And Troubleshooting Manual page 155

post min max Output Comparison (Continued)
TABLE 7-5
Output Displayed
0>Data Bitwalk on Master
0> Test Bank 0.
0>Address Bitwalk on Master
0>Addr walk mem test on CPU 0 Bank 0: 00000000.00000000 to
00000000.40000000.
0>Set Mailbox
0>Final mc1 is b0000026.3e781c61.
0>Setup Final DMMU Entries
0>Post Image Region Scrub
0>Run POST from Memory
0>Verifying checksum on copied image.
0>The Memory's CHECKSUM value is 3f81.
0>The Memory's Content Size value is 68111.
0>Success... Checksum on Memory Validated.
0>FPU Registers and Data Path
0>FPU Move Registers
0>FSR Read/Write
0>FPU Block Register Test
0>Scrub Memory
0>Quick Block Mem Test
0>Quick Test 4194304 bytes at 00000000.00600000
0>Flush Caches
0>XBus SRAM
0>IO-Bridge SouthBridge Remap Devs
0>IO-Bridge Tests.....
0>JBUS quick check
0> to IO-bridge_1
0>IO-Bridge unit 1 sram
0>IO-Bridge unit 1 reg
0>IO-Bridge unit 1 mem
0>IO-Bridge unit 1 PCI id
test
test
test
test
What Is Happening
CPU data pins are tested.
Where found, memory is tested.
CPU address pins are tested.
Mailbox register is set.
Memory control register 1 is set.
Memory is allocated for POST.
Allocated memory is set to
defaults.
POST is transferred to new
memory and executed.
Copied data is verified.
Floating point unit (FPU) is
checked.
FPU status register is checked.
Additional FPU testing is
performed.
Memory is set to zero.
A quick test of memory is made at
a particular address.
Caches are set to zero.
XBus buffer memory is checked.
I/O bridge and I/O subsystem
probe for devices.
I/O bridge is checked.
JBus communication with I/O
bridge is checked.
32K scratch pad SRAM is checked.
I/O bridge registers are checked.
I/O bridge memory is checked.
I/O bridge PCI buses are checked.
Chapter 7 Power-On Self-Test 7-11