Use Models; 1:1 Use Models; Figure 3-2: Brefclk 0:1:1 - Xilinx RocketIO X User Manual

Clock Domain Architecture

Use Models

Virtex-II Pro X MGTs have considerable flexibility of the clocking schemes. The
relationship of the BREFCLK, TXOUTCLK, RXRECCLK, RXUSRCLK, RXUSRCLK2,
Table 3-2, page
Note:
configurations. These examples can be used for REFCLK configurations, but published performance
cannot be met.
The use models discussed below the clock ratio terminology discussed in table 2-4 in
which the USRCLK:USRCLK2 is in terms of frequency. All the use models have USRCLK
or USRCLK2 as the base frequency (1); other frequencies can be 2, 4, or 0 (half the base
frequency). The models use an X:Y:Z format: X = reference clock, Y = USRCLK, and Z =
USRCLK2.
that mode.

1:1 Use models

The use models in this section represent when the external and internal data widths are the
same.
BREFCLK
USRCLK
USRCLK2 and
User Logic
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
83). The PMA modes are set by the PMA_SPEED attribute.
The examples shown in Figure 3-2
Table 3-2, page 83 shows which use model can be used for the base serial rate of

Figure 3-2: BREFCLK 0:1:1

www.xilinx.com
1-800-255-7778
through Figure 3-12 are valid for BREFCLK
DCM
CLKIN
CLK2X
CLKDV
CLK0
CLKFB
User
TX & RX
Logic
R
GT10
BREFCLK
TXOUTCLK
TXUSRCLK
BUFG
TXUSRCLK2
RXUSRCLK
BUFG
RXUSRCLK2
TXDATA
RXDATA
RXRECCLK
UG035_CH3_03_060304
75