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Note: The LED_DATA signal is now inverted from the state in Mode 0.
Figure 30. Mode 1 Timing
LED_CLK
LED_DATA
LED_LATCH
Table 33. Mode 1 Clock Cycle to Data Bit Relationship
LED_CLK Cycle
1
2:3
4:15
36:38
5.8.5
Power-On, Reset, Initialization
The LED interface is disabled at power-on or reset. The system software controller must enable the
LED interface. The internal state machines and output signals are held in reset until the full Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller device configuration is completed. This
is done by setting the LED_ENABLE bit to a logic 1 (see
page
190). The power-on default for this bit is logic 0.
5.8.6
LED DATA Decodes
The data transmitted on the LED_DATA line is determined by programming the global operation
mode as either fiber or copper.
MACs.
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
1
2
3
4
25
1
22 23 24 25 26 27 28 29 30
LED_DATA Name
LED_DATA Description
This bit has no meaning in Mode 1 operation and is shifted out of
START BIT
the 16-stage shift register chain before the LED_LATCH signal is
asserted.
These bits have no meaning in Mode 1 operation and are shifted
PAD BITS
out of the 16-stage shift register chain before the LED_LATCH
signal is asserted.
These bits are the actual data to be transmitted to the 16-stage shift
register chain. The decode for each bit in each mode is defined in
LED DATA 1-12
Table 34 on page
The data is INVERTD. Logic 1 (LED ON) = Low.
These bits have no meaning in Mode 1 operation and are latched
into positions 31 and 32 in the shift register chain. These bits are
PAD BITS
not considered as valid data and should be ignored. They should
always be a Logic 0 = High.
Table 34
shows the data decode of the data for both fiber and copper
26
27
28
29
30
31
32
119.
Table 109 "LED Control ($0x509)" on
33
34
35
®
118
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