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Table 5.
GMII Interface Signal Descriptions (Sheet 1 of 2)
Signal Name
TXD7_0
TXD6_0
TXD5_0
TXD4_0
TXD3_0
TXD2_0
TXD1_0
TXD0_0
TXD7_1
TXD6_1
TXD5_1
TXD4_1
TXD3_1
TXD2_1
TXD1_1
TXD0_1
TXD7_2
TXD6_2
TXD5_2
TXD4_2
TXD3_2
TXD2_2
TXD1_2
TXD0_2
TXD7_3
TXD6_3
TXD5_3
TXD4_3
TXD3_3
TXD2_3
TXD1_3
TXD0_3
TX_EN_0
TX_EN_1
TX_EN_2
TX_EN_3
TX_ER_0
TX_ER_1
TX_ER_2
TX_ER_3
TXC_0
TXC_1
TXC_2
TXC_3
NOTE: Refer to the RGMII interface for shared data and clock signals.
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Ball Designator
Type
Y4
AB4
AC3
AB3
AA3
Y3
Y2
Y1
AC9
AD8
AB8
AA7
AD9
AB9
AB7
AC7
Output
AA18
AA20
AB19
AD16
AB23
AB22
AB21
AB20
W14
AA16
Y15
AA14
V17
V16
V15
V14
AB2
Y8
Output
AC22
V12
W1
AD6
Output
AD17
AB13
AA1
AD7
Output
AC20
AB14
Standard
Description
Transmit Data.
Each bus carries eight data bits [7:0] of
the transmitted data stream to the PHY
device.
RGMII Mode: When a port is
configured in copper mode and the
2.5 V
RGMII interface is selected, only bits
CMOS
TXD[3:0]_n are used. The data is
transmitted on both edges of TXC_0:3.
Fiber Mode: The following signals
have multiplexed functions when a port
is configured in fiber mode:
TXD4_n: TX_DISABLE_0:3
Transmit Enable.
TX_EN indicates that valid data is
2.5 V
being driven on the corresponding
CMOS
Transmit Data: TXD_0, TXD_1, TXD_2,
and TXD_3.
Transmit Error:
2.5 V
TX_ER indicates a transmit error in the
CMOS
corresponding Transmit Data: TXD_0,
TXD_1, TXD_2, and TXD_3.
Source Synchronous Transmit
Clock.
This clock is supplied synchronous to
2.5 V
the transmit data bus in either RGMII or
CMOS
GMII mode.
NOTE: Shares the same balls as RXC
on the RGMII interface.
48
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