Port Protocol Operation; Clock And Data Transitions; Data Validity Timing; Start And Stop Definition Timing - Intel IXF1104 Datasheet

®
Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller
5.7.3.5

Port Protocol Operation

5.7.3.6

Clock and Data Transitions

2
The I C_DATA is normally pulled High with an extra device. Data on the I
only during the I
periods indicate a start or stop condition.
Figure 25. Data Validity Timing
2
I C_Data
2
I C_Clk
5.7.3.6.1
A High-to-Low transition of I
precede any other command (see
5.7.3.6.2
A Low-to-High transition of the I
sequence, the stop command places the E²PROM and the optical module in a standby power mode
(see Figure
Figure 26. Start and Stop Definition Timing
I
I
113
2
C_CLK Low time periods (see
DATA STABLE
Start Condition
2
C_DATA, with I
Figure
Stop Condition
2
C_DATA with I
26).
2
C_Data
2
C_Data
START
Figure 25). Data changes during I
DATA STABLE
DATA
CHANGE
2
C_CLK High, is a start condition that must
26).
2
C_CLK High is a stop condition. After a Read
2
C_DATA pin changes
2
C_CLK High
STOP

Datasheet

Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005