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Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
5.10.3
ID Register
The ID register is a 32-bit register. The IDCODE instruction connects this register between TDI
and TDO. See
5.10.4
Boundary Scan Register
The Boundary Scan register is a shift register made up of all the boundary scan cells associated
with the device signals. The number, type, and order of the boundary scan cells are specified in the
IXF1104 MAC BSDL file. The EXTEST and SAMPLE instructions connect this register between
TDI and TDO.
5.10.5
Bypass Register
The Bypass register is a 1-bit register that bypasses the IXF1104 MAC to reduce the JTAG chain
length when accessing other devices on the chain besides the IXF1104 MAC. The BYPASS,
HIGHZ, and CLAMP instructions connect this register between TDI and TDO.
5.11
Loopback Modes
The IXF1104 MAC provides two loopback modes for device diagnostic testing when it has been
integrated into a user system. A line-side loopback allows the line-side receive interface to be
looped back to the transmit line-side interface. A SPI3 loopback mode allows the SPI3 transmit
interface to be looped back to the SPI3 receive interface.
The IXF1104 MAC line-side and SPI3 loopback modes are effective diagnostic tools for validation
of system level connectivity and interface compatibility.
In loopback-mode operation, the data path is internally redirected to allow for the data flow return
path. Redirection requires the data path to circumvent resources that are required during normal
traffic flow. For example, while operating in SPI3 loopback mode, the data path does not pass
through the MAC or TX FIFO and those resource features are not used. The result is a possible
degradation of throughput performance and statistical data accuracy. Intel recommends that
loopback modes be used for diagnostic purposes only.
5.11.1
SPI3 Interface Loopback
To provide a diagnostic loopback feature on the SPI3 interface, it is possible to configure the
IXF1104 MAC to loop back any data written to the IXF1104 MAC through the SPI3 transmit
interface back to the SPI3 receive interface. This is accomplished using the data path shown in
Figure
33.
Note:
Loopback packets also appear on the line side TX interface.
125
Table 112 "JTAG ID ($0x50C)" on page 192
for detailed information.
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Datasheet
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