Tx Fifo Overflow/Underflow/Out Of Sequence Event ($0X61E); Datasheet - Intel IXF1104 Datasheet

Table 135. TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E) (Sheet 1 of 2)
Bit Name
Register Description: TX FIFO Out of Sequence Event:
These register bits provide status information, and indicate if out-of-sequence data has been
received. The bit position equals the port number + 8. These bits are cleared on Read.
Register Description: TX FIFO Underflow Event:
This register provides a status that a FIFO Empty situation has occurred (for example, a FIFO
under-run). The bit position equals the port number + 4. This register is cleared on Read.
Register Description: TX FIFO Overflow Event:
This register provides a status that a FIFO full situation has occurred (for example, a FIFO
overflow). The bit position equals the port number. This register is cleared on Read.
31:12 Reserved
11 FOSE3
10 FOSE2
9 FOSE1
8 FOSE0
7 FUE3
6 FUE2
5 FUE1
4 FUE0
3 FOE3
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write

Datasheet

Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller
Description
Reserved
Port 3
0 = FIFO out of sequence event did not occur
1 = FIFO out of sequence event occurred
Port 2
0 = FIFO out of sequence event did not occur
1 = FIFO out of sequence event occurred
Port 1
0 = FIFO out of sequence event did not occur
1 = FIFO out of sequence event occurred
Port 0
0 = FIFO out of sequence event did not occur
1 = FIFO out of sequence event occurred
Port 3
0 = FIFO underflow event did not occur
1 = FIFO underflow event occurred
Port 2
0 = FIFO underflow event did not occur
1 = FIFO underflow event occurred
Port 1
0 = FIFO underflow event did not occur
1 = FIFO underflow event occurred
Port 0
0 = FIFO underflow event did not occur
1 = FIFO underflow event occurred
Port 3
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred
1
Type Default
0x0
0x0
0x0
RO 0x00000
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
206