Table of Contents
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9.0
Mechanical Specifications ........................................................................................................ 224
9.1
Overview ........................................................................................................................... 224
9.1.1
Features............................................................................................................... 224
9.2
Package Specifics ............................................................................................................ 224
9.3
Package Information ......................................................................................................... 225
9.3.1
CBGA Package Diagrams ...................................................................................225
9.3.2
Flip Chip-Plastic Ball Grid Array Package Diagram .............................................227
9.3.3
Top Label Marking Example ................................................................................ 229
10.0 Product Ordering Information .................................................................................................. 230
Figures
1
Block Diagram ............................................................................................................................ 21
2
Internal Architecture....................................................................................................................22
3
552-Ball CBGA Assignments (Top View) ................................................................................... 23
4
Interface Signals ........................................................................................................................ 38
5
Power Supply Sequencing.......................................................................................................... 63
6
Analog Power Supply Filter Network ..........................................................................................65
7
Packet Buffering FIFO ................................................................................................................ 71
8
Ethernet Frame Format .............................................................................................................. 71
9
PAUSE Frame Format................................................................................................................ 72
10 Transmit Pause Control Interface ............................................................................................... 74
11 MPHY Transmit Logical Timing .................................................................................................. 85
12 MPHY Receive Logical Timing ................................................................................................... 86
13 MPHY 32-Bit Interface ................................................................................................................ 86
14 SPHY Transmit Logical Timing................................................................................................... 88
15 SPHY Receive Logical Timing .................................................................................................... 89
17 MAC GMII Interconnect .............................................................................................................. 94
18 RGMII Interface .......................................................................................................................... 96
19 TX_CTL Behavior ....................................................................................................................... 98
20 RX_CTL Behavior....................................................................................................................... 98
21 Management Frame Structure (Single-Frame Format) ............................................................ 101
22 MDI State.................................................................................................................................. 102
23 SerDes Receiver Jitter Tolerance ............................................................................................. 106
2
C Random Read Transaction................................................................................................. 111
25 Data Validity Timing ..................................................................................................................113
26 Start and Stop Definition Timing ...............................................................................................113
27 Acknowledge Timing................................................................................................................. 114
28 Random Read........................................................................................................................... 115
29 Mode 0 Timing .......................................................................................................................... 116
30 Mode 1 Timing .......................................................................................................................... 118
31 Read Timing Diagram - Asynchronous Interface ...................................................................... 121
32 Write Timing Diagram - Asynchronous Interface ...................................................................... 122
33 SPI3 Interface Loopback Path .................................................................................................. 126
34 Line Side Interface Loopback Path........................................................................................... 127
35 SPI3 Receive Interface Timing ................................................................................................. 137
36 SPI3 Transmit Interface Timing ................................................................................................ 139
Datasheet
Document Number: 278757
Revision Number: 009
®
IXF1104 MAC Ports (8-Bit Interface) ..................................... 90
Contents
7
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