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Figure 16. SPHY Connection for Two Intel
5.2.2.8.1 Clock Rates
The TFCLK and RFCLK can be independent of each other in SPHY mode operation. TFCLK and
RFCLK should be common to all the Network Processor devices. The IXF1104 MAC requires an
individual single clock source for the device transmit path and a single clock source for the device
receive path.
The IXF1104 MAC allows this interface to be overclocked so that all four IXF1104 MAC ports can
operate at 1 Gbps. This allows data transfer at data rates of up to 4.0 Gbps when operating at an
overclocked frequency of 125 MHz.
Note: SPHY operates at a maximum frequency of 125 MHz.
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
®
IXF1104 MAC Ports (8-Bit Interface)
SPI3 Bus
Network Processor
TFCLK
TENB[0]
TDAT[7:0][0]
TPRTY[0]
TSOP[0]
TEOP[0]
TERR[0]
DTPA[0]
RFCLK
RENB[0]
RDAT[7:0][0]
RPRTY[0]
RVAL[0]
RSOP[0]
REOP[0]
RERR[0]
PTPA
TADR[1:0]
TFCLK
TENB[1]
TDAT[7:0][1]
TPRTY[1]
TSOP[1]
TEOP[1]
TERR[1]
DTPA[1]
RFCLK
RENB[1]
RDAT[7:0][1]
RPRTY[1]
RVAL[1]
RSOP[1]
REOP[1]
RERR[1]
®
Intel
IXF1104
Port 0
TFCLK
TENB_0
TDAT[7:0]_0
TPRTY_0
TSOP_0
TEOP_0
TERR_0
DTPA_0
Line-Side
Transceiver
Port 0
Interface
RFCLK
RENB_0
RDAT[7:0]_0
RPRTY_0
RVAL_0
RSOP_0
REOP_0
RERR_0
SPI3
Flow Control
PTPA
TADR[1:0]
Port 1
TFCLK
TENB_1
TDAT[7:0]_1
TPRTY_1
TSOP_1
TEOP_1
TERR_1
DTPA_1
Line-Side
Transceiver
Port 1
Interface
RFCLK
RENB_1
RDAT[7:0]_1
RPRTY_1
RVAL_1
RSOP_1
REOP_1
RERR_1
B0659-02
90
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