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Figure 32. Write Timing Diagram - Asynchronous Interface
uPx_Add[12:0]
uPx_Data[31:0]
5.9.1.3
CPU Timing Parameters
For information on the CPU interface Read and Write cycle AC timing parameters, refer to
47 "CPU Interface Read Cycle AC Timing" on page
AC Timing" on page
page
150.
5.9.2
Endian
The Endian of the CPU interface may be changed to allow connection of various CPUs to the
®
Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller. The Endian selection is
determined by setting the Endian bit in the
The following describes Endianness control:
•
There is a byte swapper between the internal 32-bit bus and the external 32-bit bus.
•
In 8-bit or 16-bit mode operation, the byte packer/byte unpacker holding registers sink and
source data just like the 32-bit external bus in 32-bit mode.
•
The
"CPU Interface ($0x508)"
•
The byte swapper causes the behavior seen in
data[31:0].
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
T
CAS
uPx_CsN
uPx_WrN
uPx_RdyN
149, and
Table 54 "CPU Interface Write Cycle AC Signal Parameters" on
selects Big-Endian or Little-Endian mode.
T
CWL
T
CDWS
149,
Figure 48 "CPU Interface Write Cycle
"CPU Interface
($0x508)".
Table 37
for accessing a register with data bits
T
CAH
T
CWH
T
CDWH
T
CYD
T
CDWD
Figure
122
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