Spi3 Mphy/Sphy Ball Connections; Spi3 Mphy/Sphy Interface - Intel IXF1104 Datasheet

®
Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 16. Line Side Interface Multiplexed Balls (Sheet 2 of 2)
Copper Mode
GMII Signal
NC
NC
NC
MDC
2
MDIO
NC
NC
1. An external pull-up resistor is required with most optical modules.
2. An open drain I/O, external 4.7 k Ω pull-up resistor is required.
4.5.2

SPI3 MPHY/SPHY Ball Connections

Table 17 lists the balls used for the SPI3 Interface and provides a guide to connect these balls in
MPHY and SPHY mode.
Table 17. SPI3 MPHY/SPHY Interface (Sheet 1 of 3)
SPI3 Signals
MPHY
TDAT[31:24]
TDAT[23:16]
TDAT[15:8]
TDAT[7:0]
TFCLK
TPRTY_0
GND
GND
GND
TENB_0
VDD2
VDD2
VDD2
59
Fiber Mode
Optical Module/
RGMII Signal
SerDes Signal
NC TX_FAULT_INT
NC RX_LOS_INT
NC MOD_DEF_INT
MDC NC
2
MDIO NC
2
NC I C_CLK
2
NC I C_DATA_0:3
Ball Number
SPHY
F7 F5
TDAT[7:0]_3
G7 G6
C8 F9
TDAT[7:0]_2
E8 E7
H3 J3
TDAT[7:0]_1
H1 G2
C6 B5
TDAT[7:0]_0
D1 C3
TFCLK D7
TPRTY_0 D5
TPRTY_1 G3
TPRTY_2 B9
TPRTY_3 J6
TENB_0 B7
TENB_1 E2
TENB_2 C9
TENB_3 J4
Unused Port
2
NC P23
2
NC P19
2
NC N22
NC W24
NC V21
NC L23
2
NC L24
G9 G8
G5 G4
E10 E9
MPHY: Consists of a single 32-bit data
E6 E5
bus
SPHY: Separate 8-bit data bus for each
J2 J1
Ethernet port
G1 F1
C5 C4
C2 B3
To achieve maximum bandwidth, set
TFCLK as follows:
MPHY: 133 MHz
SPHY: 125 MHz.
MPHY: Use TPRTY_0 as the TPRTY
signal.
SPHY: Each port has its own dedicated
TPRTY_n signal.
MPHY: Use TENB_0 as the TENB
signal.
SPHY: Each port has its own dedicated
TENB_n signal.
Ball Designator
M24 N24 P24
Comments
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005